T13/1532D Volume 3 Revision 0 Table 21-Signal assignments for 50-pin 2.5 inch form factor style connector Signal name Connector Conductor Connector Signal name contact contact Option selection pins A B Option selection pins Option selection pins D Option selection pins (keypin) E F (keypin) RESET- 1 1 2 2 Ground DD7 3 3 4 4 DD8 DD6 5 5 6 6 DD9 DD5 7 7 8 8 DD10 DD4 9 9 10 10 DD11 DD3 11 11 12 12 DD12 DD2 13 13 14 14 DD13 DD1 15 15 16 16 DD14 DDO 17 17 18 18 DD15 Ground 19 19 20 20 (keypin) DMARQ 21 21 22 22 Ground DIOW-:STOP 23 23 24 24 Ground DIOR-:HDMARDY- 25 25 26 26 Ground HSTROBE JORDY:DDMARDY. 27 27 28 28 CSEL :DSTROBE DMACK- 29 29 30 30 Ground INTRQ 31 31 32 32 Obsolete (see note) DA1 33 33 34 34 PDIAG- DA0 35 35 36 36 DA2 CS0- 37 37 38 38 CS1- DASP- 39 39 40 40 Ground +5 V(logic) 41 41 42 42 +5V(motor) Ground(return) 43 43 44 44 Reserved-no connection NOTE-Pin 32 was defined as IOCS16 in ATA-2,ANSI X3.279-1996. 2.3.5 68-pin PCMCIA connector This clause defines the pinouts used for the 68-pin alternative connector for the AT Attachment Interface.This connector is defined in the PCMCIA PC Card Standard.This clause defines a pinout alternative that allows a device to function as an AT Attachment Interface compliant device,while also allowing the device to be compliant with PC Card ATA mode defined by PCMCIA.The signal protocol allows the device to identify the host interface as being 68-pin as defined in this standard or PC Card ATA. To simplify the implementation of dual-interface devices,the 68-pin AT Attachment Interface maintains commonality with as many PC Card ATA signals as possible,while supporting full command and signal compliance with this standard. The 68-pin pinout shall not cause damage or loss of data if a PCMCIA card is accidentally plugged into a host slot supporting this interface.The inversion of the RESET signal between this standard and PCMCIA interfaces prevents loss of data if the device is unable to reconfigure itself to the appropriate host interface. 2.3.5.1 Signals This specification relies upon the electrical and mechanical characteristics of PCMCIA and unless otherwise noted,all signals and registers with the same names as PCMCIA signals and registers have the same meaning as defined in PCMCIA. Page 24
T13/1532D Volume 3 Revision 0 Page 24 Table 21 − Signal assignments for 50-pin 2.5 inch form factor style connector Signal name Connector contact Conductor Connector contact Signal name Option selection pins A B Option selection pins Option selection pins C D Option selection pins (keypin) E F (keypin) RESET- 1 1 2 2 Ground DD7 3 3 4 4 DD8 DD6 5 5 6 6 DD9 DD5 7 7 8 8 DD10 DD4 9 9 10 10 DD11 DD3 11 11 12 12 DD12 DD2 13 13 14 14 DD13 DD1 15 15 16 16 DD14 DD0 17 17 18 18 DD15 Ground 19 19 20 20 (keypin) DMARQ 21 21 22 22 Ground DIOW-:STOP 23 23 24 24 Ground DIOR-:HDMARDY- :HSTROBE 25 25 26 26 Ground IORDY:DDMARDY- :DSTROBE 27 27 28 28 CSEL DMACK- 29 29 30 30 Ground INTRQ 31 31 32 32 Obsolete (see note) DA1 33 33 34 34 PDIAGDA0 35 35 36 36 DA2 CS0- 37 37 38 38 CS1- DASP- 39 39 40 40 Ground +5 V (logic) 41 41 42 42 +5 V (motor) Ground(return) 43 43 44 44 Reserved - no connection NOTE − Pin 32 was defined as IOCS16 in ATA-2, ANSI X3.279-1996. 2.3.5 68-pin PCMCIA connector This clause defines the pinouts used for the 68-pin alternative connector for the AT Attachment Interface. This connector is defined in the PCMCIA PC Card Standard. This clause defines a pinout alternative that allows a device to function as an AT Attachment Interface compliant device, while also allowing the device to be compliant with PC Card ATA mode defined by PCMCIA. The signal protocol allows the device to identify the host interface as being 68-pin as defined in this standard or PC Card ATA. To simplify the implementation of dual-interface devices, the 68-pin AT Attachment Interface maintains commonality with as many PC Card ATA signals as possible, while supporting full command and signal compliance with this standard. The 68-pin pinout shall not cause damage or loss of data if a PCMCIA card is accidentally plugged into a host slot supporting this interface. The inversion of the RESET signal between this standard and PCMCIA interfaces prevents loss of data if the device is unable to reconfigure itself to the appropriate host interface. 2.3.5.1 Signals This specification relies upon the electrical and mechanical characteristics of PCMCIA and unless otherwise noted, all signals and registers with the same names as PCMCIA signals and registers have the same meaning as defined in PCMCIA
T13/1532D Volume 3 Revision 0 The PC Card ATA specification is used as a reference to identify the signal protocol used to identify the host interface protocol. 2.3.5.2 Signal descriptions Any signals not defined below shall be as described in this standard,PCMCIA,or the PC Card ATA documents. Table 22 shows the signals and relationships such as direction,as well as providing the signal name of the PCMCIA equivalent. Page 25
T13/1532D Volume 3 Revision 0 Page 25 The PC Card ATA specification is used as a reference to identify the signal protocol used to identify the host interface protocol. 2.3.5.2 Signal descriptions Any signals not defined below shall be as described in this standard, PCMCIA, or the PC Card ATA documents. Table 22 shows the signals and relationships such as direction, as well as providing the signal name of the PCMCIA equivalent
T13/1532D Volume 3 Revision 0 Table 22-Signal assignments for 68-pin connector Pin Signal Hst Dir Dev PCMCIA Pin Signal Hst Dir Dev PCMCIA 1 Ground X Ground 35 Ground X Ground 2 DD3 + ←) + D3 36 CD1- X ←- X CD1- 3 DD4 ←) + D4 37 DD11 X ← X D11 4 DD5 ←) D5 38 DD12 ←→ × D12 夕 DD6 ←→ X D6 39 DD13 ←) X D13 6 DD7 ←→ D7 40 DD14 X ←) D14 CSO- X X CE1- 41 DD15 X ←→ X D15 8 i A10 42 CS1- X x(1) CE2- 9 SELATA- X OE- 43 i VS1- 10 44 DIOR- X X IORD- 11 CS1- X→ x(1) A9 45 DIOW- X X IOWR- 12 i A8 46 13 47 14 48 15 i WE- 49 16 INTRO X←- READY/ 50 IREQ- 17 Vcc X→X Vcc 51 Vcc X→ Vcc 18 52 19 53 20 54 21 55 M/S- X →X(2) 22 ) i A7 56 CSEL X x(2) 23 A6 57 i VS2- 24 A5 58 RESET- RESET 25 i A4 59 JORDY 0 ←- X(3) WAIT- 26 i A3 60 DMARQ 0 ←- x(3) INPACK- 27 DA2 → A2 61 DMACK- 0 0 REG- 28 DA1 A1 62 DASP- BVD2/ SPKR- 29 DAO →X A0 63 PDIAG- X ←→ BVD1/ STSCHG 30 DDO → X DO 64 DD8 X ←→ X D8 31 DD1 X ←) X D1 65 DD9 X ←→ X D9 32 DD2 X () X D2 66 DD10 X ←) X D10 33 WP/ 67 CD2- X X CD2- 1O1S16 34 Ground X→ X Ground 68 Ground X X Ground Key: Dir the direction of the sianal between host and device. x in the Hst column this signal shall be supported by the Host. x in the Dev column this signal shall be supported by the device. i in the Dev column=this signal shall be ignored by the device while in 68-pin mode. o this signal is Optional. Nothing in Dev column no connection should be made to that pin. NOTES- 1 The device shall support only one CS1-signal pin. 2 The device shall support either M/S-or CSEL but not both. 3 The device shall hold this signal negated if it does not support the function. Page 26
T13/1532D Volume 3 Revision 0 Page 26 Table 22 − Signal assignments for 68-pin connector Pin Signal Hst Dir Dev PCMCIA Pin Signal Hst Dir Dev PCMCIA 1 Ground x → x Ground 35 Ground x → x Ground 2 DD3 x ↔ x D3 36 CD1- x ← x CD1- 3 DD4 x ↔ x D4 37 DD11 x ↔ x D11 4 DD5 x ↔ x D5 38 DD12 x ↔ x D12 5 DD6 x ↔ x D6 39 DD13 x ↔ x D13 6 DD7 x ↔ x D7 40 DD14 x ↔ x D14 7 CS0- x → x CE1- 41 DD15 x ↔ x D15 8 → i A10 42 CS1- x → x(1) CE2- 9 SELATA- x → x OE- 43 ← i VS1- 10 44 DIOR- x → x IORD- 11 CS1- x → x(1) A9 45 DIOW- x → x IOWR- 12 → i A8 46 13 47 14 48 15 → i WE- 49 16 INTRQ x ← x READY/ IREQ- 50 17 Vcc x → x Vcc 51 Vcc x → x Vcc 18 52 19 53 20 54 21 55 M/S- x → x(2) 22 → i A7 56 CSEL x → x(2) 23 → i A6 57 ← i VS2- 24 → i A5 58 RESET- x → x RESET 25 → i A4 59 IORDY o ← x(3) WAIT- 26 → i A3 60 DMARQ o ← x(3) INPACK- 27 DA2 x → x A2 61 DMACK- o → o REG- 28 DA1 x → x A1 62 DASP- x ↔ x BVD2/ SPKR- 29 DA0 x → x A0 63 PDIAG- x ↔ x BVD1/ STSCHG 30 DD0 x ↔ x D0 64 DD8 x ↔ x D8 31 DD1 x ↔ x D1 65 DD9 x ↔ x D9 32 DD2 x ↔ x D2 66 DD10 x ↔ x D10 33 x ← x WP/ IOIS16 67 CD2- x ← x CD2- 34 Ground x → x Ground 68 Ground x → x Ground Key: Dir = the direction of the signal between host and device. x in the Hst column = this signal shall be supported by the Host. x in the Dev column = this signal shall be supported by the device. i in the Dev column = this signal shall be ignored by the device while in 68-pin mode. o = this signal is Optional. Nothing in Dev column = no connection should be made to that pin. NOTES − 1 The device shall support only one CS1- signal pin. 2 The device shall support either M/S- or CSEL but not both. 3 The device shall hold this signal negated if it does not support the function
T13/1532D Volume 3 Revision 0 2.3.5.2.1 CD1-(Card Detect 1) This signal shall be grounded by the device.CD1-and CD2-are used by the host to detect the presence of the device. 2.3.5.2.2 CD2-(Card Detect 2) This signal shall be grounded by the device.CD1-and CD2-are used by the host to detect the presence of the device. 2.3.5.2.3 CS1-(Device chip select 1) Hosts shall provide CS1-on both the pins identified in Table 22. Devices shall recognize only one of the two pins as CS1-. 2.3.5.2.4 DMACK-(DMA acknowledge) This signal is optional for hosts and devices. If this signal is supported by the host or the device,the function of DMARQ shall also be supported. 2.3.5.2.5 DMARQ (DMA request) This signal is optional for hosts. If this signal is supported by the host or the device,the function of DMACK-shall also be supported. 2.3.5.2.6 IORDY (l/O channel ready) This signal is optional for hosts. 2.3.5.2.7 M/S-(Master/slave) This signal is the inverted form of CSEL.Hosts shall support both M/S-and CSEL though devices need only support one or the other. Hosts shall assert CSEL and M/S-prior to applying VCC to the connector. 2.3.5.2.8 SELATA-(Select 68-pin ATA) This pin is used by the host to select which mode to use.PC Card ATA mode or the 68-pin mode defined in this standard.To select 68-pin ATA mode,the host shall assert SELATA-prior to applying power to the connector,and shall hold SELATA-asserted. The device shall not re-sample SELATA-as a result of either a hardware or software reset.The device shall ignore all interface signals for 19 ms after the host supplies Vcc within the device's voltage tolerance.If SELATA-is negated following this time,the device shall either configure itself for PC Card ATA mode or not respond to further inputs from the host. 2.3.5.3 Removability considerations Page 27
T13/1532D Volume 3 Revision 0 Page 27 2.3.5.2.1 CD1- (Card Detect 1) This signal shall be grounded by the device. CD1- and CD2- are used by the host to detect the presence of the device. 2.3.5.2.2 CD2- (Card Detect 2) This signal shall be grounded by the device. CD1- and CD2- are used by the host to detect the presence of the device. 2.3.5.2.3 CS1- (Device chip select 1) Hosts shall provide CS1- on both the pins identified in Table 22. Devices shall recognize only one of the two pins as CS1-. 2.3.5.2.4 DMACK- (DMA acknowledge) This signal is optional for hosts and devices. If this signal is supported by the host or the device, the function of DMARQ shall also be supported. 2.3.5.2.5 DMARQ (DMA request) This signal is optional for hosts. If this signal is supported by the host or the device, the function of DMACK- shall also be supported. 2.3.5.2.6 IORDY (I/O channel ready) This signal is optional for hosts. 2.3.5.2.7 M/S- (Master/slave) This signal is the inverted form of CSEL. Hosts shall support both M/S- and CSEL though devices need only support one or the other. Hosts shall assert CSEL and M/S- prior to applying VCC to the connector. 2.3.5.2.8 SELATA- (Select 68-pin ATA) This pin is used by the host to select which mode to use, PC Card ATA mode or the 68-pin mode defined in this standard. To select 68-pin ATA mode, the host shall assert SELATA- prior to applying power to the connector, and shall hold SELATA- asserted. The device shall not re-sample SELATA- as a result of either a hardware or software reset. The device shall ignore all interface signals for 19 ms after the host supplies Vcc within the device's voltage tolerance. If SELATA- is negated following this time, the device shall either configure itself for PC Card ATA mode or not respond to further inputs from the host. 2.3.5.3 Removability considerations
T13/1532D Volume 3 Revision 0 This specification supports the removability of devices that use the protocol.As removability is a new consideration for devices,several issues need to be considered with regard to the insertion or removal of devices. 2.3.5.3.1 Device recommendations The following are recommendations to device implementors: CS0-,CS1-,RESET-,and SELATA-signals be negated on the device to prevent false selection during hot insertion. Ignore all interface signals except SELATA-until 19 ms after the host supplies c within the device's voltage tolerance.This time is necessary to de-bounce the device's power-on reset sequence.Once in the 68-pin mode as defined in this standard,if SELATA-is ever negated following the 19 ms de-bounce delay time,the device disables itself until Vcc is removed. Provide a method to prevent unexpected removal of the device or media. 2.3.5.3.2 Host recommendations The following are recommendations to host implementors: Connector pin sequencing to protect the device by making contact to ground before any other signal in the system. SELATA-to be asserted at all times. All devices reset and reconfigured to the same base address each time a device at that address is inserted or removed. -The removal or insertion of a device at the same address to be detected so as to prevent the corruption of a command. Provide a method to prevent unexpected removal of the device or media. 2.3.6 CompactFlashTM connector Device compliant with the CompactFlashTM Association Specification use the connector defined in that specification. 2.3.7 1.8 inch 3.3V parallel connector The connector for the 1.8 inch 3.3V parallel form factor device is defined in Figure 15 with dimensions defines in Table 23.Pin assignments are defined in Table 24. Page 28
T13/1532D Volume 3 Revision 0 Page 28 This specification supports the removability of devices that use the protocol. As removability is a new consideration for devices, several issues need to be considered with regard to the insertion or removal of devices. 2.3.5.3.1 Device recommendations The following are recommendations to device implementors: − CS0-, CS1-, RESET-, and SELATA- signals be negated on the device to prevent false selection during hot insertion. − Ignore all interface signals except SELATA- until 19 ms after the host supplies VCC within the device's voltage tolerance. This time is necessary to de-bounce the device's power-on reset sequence. Once in the 68-pin mode as defined in this standard, if SELATA- is ever negated following the 19 ms de-bounce delay time, the device disables itself until VCC is removed. − Provide a method to prevent unexpected removal of the device or media. 2.3.5.3.2 Host recommendations The following are recommendations to host implementors: − Connector pin sequencing to protect the device by making contact to ground before any other signal in the system. − SELATA- to be asserted at all times. − All devices reset and reconfigured to the same base address each time a device at that address is inserted or removed. − The removal or insertion of a device at the same address to be detected so as to prevent the corruption of a command. − Provide a method to prevent unexpected removal of the device or media. 2.3.6 CompactFlash connector Device compliant with the CompactFlash Association Specification use the connector defined in that specification. 2.3.7 1.8 inch 3.3V parallel connector The connector for the 1.8 inch 3.3V parallel form factor device is defined in Figure 15 with dimensions defines in Table 23. Pin assignments are defined in Table 24