《计算机维护维修 Computer Load & Repair》课程教学资源（文献资料）Information Technology - AT Attachment with Packet Interface – 7 Volume 3（ATA/ATAPI-7 V3）.pdf_P16-P20

T13/1532D Volume 3 Revision 0 Table 3-AC characteristics Description Min Max SRISE Rising edge slew rate for any signal(see note 1) 1.25 V/ns SFALL Falling edge slew rate for any signal(see note 1) 1.25 V/ns Chost Host interface signal capacitance at the host connector(see note 4) 25 pf Cdevice Device interface signal capacitance at the device connector (see 20pf note 4) Additional AC characteristics for Ultra DMA modes greater than mode 4 SRISE2 Rising edge slew rate for DD(15:0)and STROBE (see note 1) 0.40 V/ns 1.0 V/ns SFALL2 Falling edge slew rate for DD(15:0)and STROBE (see note 1) 0.40 V/ns 1.0 V/ns VDSSoH Induced signal to conductor side of device connector for any non- VoD3-500 switching data signal at Vh due to simultaneous switching of all mV other data lines high and low by the device (see note 2) VpssoL Same as VossoH except non-switching data signal at VL (see note 500mV 2) VHSSOH Induced signal to conductor side of host connector for any non- V0o3-600 switching data signal at V due to simultaneous switching of all mV other data lines high and low by the host(see note 2) VHSSOL Same as VHssoH except non-switching data signal at VaL (see note 600mV 2 VRING AC voltage at recipient connector(see note 3) -1V 6V Cdevice2 Device capacitance measured at the connector pin(see note 4) 17 pf Cratio Ratio of the highest DD(15:0)or STROBE signal capacitance as 1.5 measured at the connector to the lowest DD(15:0)or STROBE signal capacitance. NOTES- 1 The sender shall be tested while driving an 18"long,80-conductor cable with PVC insulation material. The signal under test shall be cut at a test point so that it has no trace,cable,or recipient loading after the test point.All other signals should remain connected through to the recipient.The test point may be located at any point between the sender's series termination resistor and 0.5"or less of conductor exiting the connector.If the test point is on a cable conductor rather than the PCB,an adjacent ground conductor shall also be cut within 0.5"of the connector.The test load and test points should then be soldered directly to the exposed source side connectors.The test load consists of a 15 or 40 pf,5%, 0.08"by 0.05"surface mount or smaller size,capacitor from the test point to ground.Slew rates shall be met for both capacitor values.Measurements shall be taken at the test point using a <1 pf,>100 k.1 GHz or faster probe and a 500 MHz or faster oscilloscope.The average rate shall be measured from 20 to 80%of the settled V level with data transitions at least 120 ns apart.The settled VoH level shall be measured as the average output high level under the defined testing conditions from 100 ns after 80%of a rising edge until 20%of the subsequent falling edge. 2 Vaso shall be tested with the same test cable configuration as described in note 1 for slew rate except with the test load described here and the cut-cable-conductor configuration.For both VL and VH measurements,the test load shall consist of a 90.9 1%resistor and a 0.1 uf 20%capacitor in series to ground.Both resistor and capacitor shall be 0.08"by 0.05"surface mount or smaller size.The order of components should be signal-resistor-capacitor-ground.Refer to 4.2.2.3 for PCB layout requirements related to Vsso. 3 The sender shall not generate voltage peaks higher then these absolute limits on any data line DD(15:0) with all data lines switching simultaneously and a single recipient at end of cable.The test load shall be an 18"long,40-conductor cable operated in Ultra DMA mode 2,as well as,an 18",long 80- conductor cable operated in the highest Ultra DMA mode supported. 4 Capacitance measured at 1 MHz. Page5

T13/1532D Volume 3 Revision 0 Page 5 Table 3 − AC characteristics Description Min Max SRISE Rising edge slew rate for any signal (see note 1) 1.25 V/ns SFALL Falling edge slew rate for any signal (see note 1) 1.25 V/ns Chost Host interface signal capacitance at the host connector (see note 4) 25 pf Cdevice Device interface signal capacitance at the device connector (see note 4) 20 pf Additional AC characteristics for Ultra DMA modes greater than mode 4 SRISE2 Rising edge slew rate for DD(15:0) and STROBE (see note 1) 0.40 V/ns 1.0 V/ns SFALL2 Falling edge slew rate for DD(15:0) and STROBE (see note 1) 0.40 V/ns 1.0 V/ns VDSSOH Induced signal to conductor side of device connector for any nonswitching data signal at VoH due to simultaneous switching of all other data lines high and low by the device (see note 2) VDD3 – 500 mV VDSSOL Same as VDSSOH except non-switching data signal at VoL (see note 2) 500 mV VHSSOH Induced signal to conductor side of host connector for any nonswitching data signal at VoH due to simultaneous switching of all other data lines high and low by the host (see note 2) VDD3 – 600 mV VHSSOL Same as VHSSOH except non-switching data signal at VoL (see note 2) 600 mV VRING AC voltage at recipient connector (see note 3) -1 V 6 V Cdevice2 Device capacitance measured at the connector pin (see note 4) 17 pf Cratio Ratio of the highest DD(15:0) or STROBE signal capacitance as measured at the connector to the lowest DD(15:0) or STROBE signal capacitance. 1.5 NOTES – 1 The sender shall be tested while driving an 18” long, 80-conductor cable with PVC insulation material. The signal under test shall be cut at a test point so that it has no trace, cable, or recipient loading after the test point. All other signals should remain connected through to the recipient. The test point may be located at any point between the sender's series termination resistor and 0.5" or less of conductor exiting the connector. If the test point is on a cable conductor rather than the PCB, an adjacent ground conductor shall also be cut within 0.5" of the connector. The test load and test points should then be soldered directly to the exposed source side connectors. The test load consists of a 15 or 40 pf, 5%, 0.08” by 0.05” surface mount or smaller size, capacitor from the test point to ground. Slew rates shall be met for both capacitor values. Measurements shall be taken at the test point using a <1 pf, >100 kΩ, 1 GHz or faster probe and a 500 MHz or faster oscilloscope. The average rate shall be measured from 20 to 80% of the settled VoH level with data transitions at least 120 ns apart. The settled VoH level shall be measured as the average output high level under the defined testing conditions from 100 ns after 80% of a rising edge until 20% of the subsequent falling edge. 2 Vsso shall be tested with the same test cable configuration as described in note 1 for slew rate except with the test load described here and the cut-cable-conductor configuration. For both VoL and VoH measurements, the test load shall consist of a 90.9 Ω 1% resistor and a 0.1 µf 20% capacitor in series to ground. Both resistor and capacitor shall be 0.08” by 0.05” surface mount or smaller size. The order of components should be signal-resistor-capacitor-ground. Refer to 4.2.2.3 for PCB layout requirements related to VSSO. 3 The sender shall not generate voltage peaks higher then these absolute limits on any data line DD(15:0) with all data lines switching simultaneously and a single recipient at end of cable. The test load shall be an 18" long, 40-conductor cable operated in Ultra DMA mode 2, as well as, an 18", long 80- conductor cable operated in the highest Ultra DMA mode supported. 4 Capacitance measured at 1 MHz

T13/1532D Volume 3 Revision 0 2.2.1 Driver types and required termination Table 4-Driver types and required termination Signal Source Driver type Host Device Notes (see note 1) (see note 2) (see note 2) RESET- Host TP DD(15:0) Bidir TS 3 DMARQ Device TS 5.6 kQ PD DIOR-:HDMARDY- Host TS :HSTROBE DIOW-:STOP Host TS IORDY:DDMARDY- Device TS 4.7 kQ PU 6,10 :DSTROBE CSEL Host Ground 10kΩPU 4,6 DMACK- Host TP INTRQ Device TS 10k2 5 DA(2:0) Host TP PDIAG-:CBLID- Device TS 10 k2 PU 26,7.8 CS0-CS1- Host TP DASP- Device OC 10 k2 PU 6,9 NOTES- 1 TS=Tri-state;OC=Open Collector;TP=Totem-pole;PU=Pull-up;PD=Pull-down. 2 All resistor values are the minimum(lowest allowed)except for the 10 k PU on PDIAG-:CBLID-which shall have a tolerance of t5%or less. 3 Devices shall not have a pull-up resistor on DD7.The host shall have a 10 k pull-down resistor and not a pull-up resistor on DD7 to allow a host to recognize the absence of a device at power-up so that a host shall detect BSY as being cleared when attempting to read the Status register of a device that is not present. 4 When used as CSEL,this line is grounded at the host and a 10 k pull-up is required at both devices. 5 A 10 k pull-down or pull-up,depending upon the level sensed,should be implemented at the host. 6 Pull-up values are based on +5 V Vcc.Except for the pull-up on PDIAG-:CBLID-which shall be to +5 Vcc for backward compatibility,pull-ups may be to VoD3.For systems supporting Ultra DMA modes greater than 4,the host pull-up on IORDY:DDMARDY-:DSTROBE should be to VoD3. 7 Hosts that do not support Ultra DMA modes greater than mode 2 shall not connect to the PDIAG- :CBLID-signal. 8 The 80-conductor cable assembly shall meet the following requirements:the PDIAG-:CBLID-signal shall be connected to ground in the host connector of the cable assembly:the PDIAG-:CBLID- signal shall not be connected between the host and the devices;and,the PDIAG-:CBLID-signal shall be connected between the devices. 9 The host shall not drive DASP-.If the host connects to DASP-for any purpose,the host shall ensure that the signal level detected on the interface for DASP-shall maintain Vh and Vo compatibility, given the l and lo requirements of the DASP-device drivers. 10 For host systems not supporting modes greater than Ultra DMA mode 4,a pull-up of 1 k may be used. 2.2.2 Electrical characteristics for Ultra DMA Hosts that support Ultra DMA transfer modes greater than mode 2 shall not share signals between primary and secondary 1/O ports.They shall provide separate drivers and separate receivers for each cable. Page 6

T13/1532D Volume 3 Revision 0 Page 6 2.2.1 Driver types and required termination Table 4 − Driver types and required termination Signal Source Driver type (see note 1) Host (see note 2) Device (see note 2) Notes RESET- Host TP DD(15:0) Bidir TS 3 DMARQ Device TS 5.6 kΩ PD DIOR-:HDMARDY- :HSTROBE Host TS DIOW-:STOP Host TS IORDY:DDMARDY- :DSTROBE Device TS 4.7 kΩ PU 6,10 CSEL Host Ground 10 kΩ PU 4, 6 DMACK- Host TP INTRQ Device TS 10 kΩ 5 DA(2:0) Host TP PDIAG-:CBLID- Device TS 10 kΩ PU 2,6,7,8 CS0- CS1- Host TP DASP- Device OC 10 kΩ PU 6,9 NOTES − 1 TS=Tri-state; OC=Open Collector; TP=Totem-pole; PU=Pull-up; PD=Pull-down. 2 All resistor values are the minimum (lowest allowed) except for the 10 kΩ PU on PDIAG-:CBLID- which shall have a tolerance of ±5% or less. 3 Devices shall not have a pull-up resistor on DD7. The host shall have a 10 kΩ pull-down resistor and not a pull-up resistor on DD7 to allow a host to recognize the absence of a device at power-up so that a host shall detect BSY as being cleared when attempting to read the Status register of a device that is not present. 4 When used as CSEL, this line is grounded at the host and a 10 kΩ pull-up is required at both devices. 5 A 10 kΩ pull-down or pull-up, depending upon the level sensed, should be implemented at the host. 6 Pull-up values are based on +5 V Vcc. Except for the pull-up on PDIAG-:CBLID- which shall be to +5 VCC for backward compatibility, pull-ups may be to VDD3. For systems supporting Ultra DMA modes greater than 4, the host pull-up on IORDY:DDMARDY-:DSTROBE should be to VDD3. 7 Hosts that do not support Ultra DMA modes greater than mode 2 shall not connect to the PDIAG- :CBLID- signal. 8 The 80-conductor cable assembly shall meet the following requirements: the PDIAG-:CBLID- signal shall be connected to ground in the host connector of the cable assembly; the PDIAG-:CBLIDsignal shall not be connected between the host and the devices; and, the PDIAG-:CBLID- signal shall be connected between the devices. 9 The host shall not drive DASP-. If the host connects to DASP- for any purpose, the host shall ensure that the signal level detected on the interface for DASP- shall maintain VoH and VoL compatibility, given the IoH and IoL requirements of the DASP- device drivers. 10 For host systems not supporting modes greater than Ultra DMA mode 4, a pull-up of 1 kΩ may be used. 2.2.2 Electrical characteristics for Ultra DMA Hosts that support Ultra DMA transfer modes greater than mode 2 shall not share signals between primary and secondary I/O ports. They shall provide separate drivers and separate receivers for each cable

T13/1532D Volume 3 Revision 0 2.2.2.1 Cable configuration The following table defines the host transceiver configurations for a dual cable system configuration for all transfer modes. Transfer Optional host Recommended host Mandatory host mode transceiver configuration transceiver configuration transceiver configuration All PIO and One transceiver may be used DIOR-,DIOW-,and IORDY Either DIOR-,DIOW-,and Multiword DMA for signals to both ports. should have a separate IORDY or CS0-and CS1- transceiver for each port. shall have a separate transceiver for each port. Ultra DMA One transceiver may be used DIOR-,DIOW-,and IORDY Either DIOR-,DIOW-,and 0,1,2 for signals to both ports should have a separate IORDY or CS0-and CS1- except DMACK-. transceiver for each port. shall have a separate transceiver for each port. DMACK-shall have a separate transceiver for each port. Ultra DMA One transceiver may be used RESET-,INTRQ,DA(2:0). All signals shall have a modes >2 for signals to both ports for CS0-,CS1-,and DASP. separate transceiver for RESET-,INTRQ,DA(2:0), should have a separate each port except for CSO-,CS1-,and DASP-. transceiver for each port. RESET-,INTRQ,DA(2:0). CS0-,CS1-,and DASP-. The following table defines the system configuration for connection between devices and systems for all transfer modes. Transfer Single device direct 40-conductor cable 80-conductor cable mode connection configuration connection configuration connection configuration (see note 1) (see note 2) (see note 2) All PIO and May be used. May be used. May be used(see note 3) Multiword DMA Ultra DMA May be used. May be used. May be used(see note 3) 0.1,2 Ultra DMA May be used (see note 4). Shall not be used. May be used(see note 4). modes>2 NOTES- 1 Direct connection is a direct point-to-point connection between the host connector and the device connector. 2 The 40-conductor cable assembly and the 80-conductor cable assembly are defined in 2.3. 3 80-conductor cable assemblies may be used in place of 40-conductor cable assemblies to improve signal quality for data transfer modes that do not require an 80-conductor cable assembly. 4 Either a single device direct connection configuration or an 80-conductor cable connection configuration shall be used for systems operating with Ultra DMA modes greater than 2. 2.2.2.2 Series termination required for Ultra DMA Series termination resistors are required at both the host and the device for operation in any of the Ultra DMA modes.Table 5 describes typical values for series termination at the host and the device. For host systems and devices supporting Ultra DMA modes greater than 4,the output and bi-directional series termination values for DD(15:0)and STROBE signals shall be chosen so that the sum of the driver output resistance at Va2 or VoH2 and the series termination resistance is between 50 and 85 For these systems, the STROBE input shall use the same series termination resistance value as the data lines. Page 7

T13/1532D Volume 3 Revision 0 Page 7 2.2.2.1 Cable configuration The following table defines the host transceiver configurations for a dual cable system configuration for all transfer modes. Transfer mode Optional host transceiver configuration Recommended host transceiver configuration Mandatory host transceiver configuration All PIO and Multiword DMA One transceiver may be used for signals to both ports. DIOR-, DIOW-, and IORDY should have a separate transceiver for each port. Either DIOR-, DIOW-, and IORDY or CS0- and CS1- shall have a separate transceiver for each port. Ultra DMA 0, 1, 2 One transceiver may be used for signals to both ports except DMACK-. DIOR-, DIOW-, and IORDY should have a separate transceiver for each port. Either DIOR-, DIOW-, and IORDY or CS0- and CS1- shall have a separate transceiver for each port. DMACK- shall have a separate transceiver for each port. Ultra DMA modes > 2 One transceiver may be used for signals to both ports for RESET-, INTRQ, DA(2:0), CS0-, CS1-, and DASP-. RESET-, INTRQ, DA(2:0), CS0-, CS1-, and DASPshould have a separate transceiver for each port. All signals shall have a separate transceiver for each port except for RESET-, INTRQ, DA(2:0), CS0-, CS1-, and DASP-. The following table defines the system configuration for connection between devices and systems for all transfer modes. Transfer mode Single device direct connection configuration (see note 1) 40-conductor cable connection configuration (see note 2) 80-conductor cable connection configuration (see note 2) All PIO and Multiword DMA May be used. May be used. May be used (see note 3) Ultra DMA 0, 1, 2 May be used. May be used. May be used (see note 3) Ultra DMA modes > 2 May be used (see note 4). Shall not be used. May be used (see note 4). NOTES – 1 Direct connection is a direct point-to-point connection between the host connector and the device connector. 2 The 40-conductor cable assembly and the 80-conductor cable assembly are defined in 2.3. 3 80-conductor cable assemblies may be used in place of 40-conductor cable assemblies to improve signal quality for data transfer modes that do not require an 80-conductor cable assembly. 4 Either a single device direct connection configuration or an 80-conductor cable connection configuration shall be used for systems operating with Ultra DMA modes greater than 2. 2.2.2.2 Series termination required for Ultra DMA Series termination resistors are required at both the host and the device for operation in any of the Ultra DMA modes. Table 5 describes typical values for series termination at the host and the device. For host systems and devices supporting Ultra DMA modes greater than 4, the output and bi-directional series termination values for DD(15:0) and STROBE signals shall be chosen so that the sum of the driver output resistance at VoL2 or VoH2 and the series termination resistance is between 50 and 85 Ω. For these systems, the STROBE input shall use the same series termination resistance value as the data lines