Line Replacement on Misses in Directed Caches If cache misses Retrieve the requested block from the next level in the memory hierarchy Store the new block in one of the cache lines of the set indicated by the set index bits
16 Line Replacement on Misses in Directed Caches • If cache misses – Retrieve the requested block from the next level in the memory hierarchy – Store the new block in one of the cache lines of the set indicated by the set index bits
Line Replacement on Misses in Directed Caches If the set is full of valid cache lines One of the existing lines must be evicted For a direct-mapped caches Each set contains only one line Current line is replaced by the newly fetched line
17 Line Replacement on Misses in Directed Caches • If the set is full of valid cache lines – One of the existing lines must be evicted • For a direct-mapped caches – Each set contains only one line – Current line is replaced by the newly fetched line
Direct-mapped cache simulation P492 M=16 byte addresses B=2 bytes/block, S=4 sets, E=1 entry/set
18 Direct-mapped cache simulation P492 • M=16 byte addresses • B=2 bytes/block, S=4 sets, E=1 entry/set
Direct-mapped cache simulation P493 M=16 byte addresses, B=2 bytes/block, s=4 sets, E=1 entry /set t=1 S=2 b=1 Address trace(reads) 0[0000]1[000113[1101]8[1000]0[000] 0 [0000](miss) 13[1101mis) tag data tag data 0m[1]m[0 10m[1]m[o] (2) 11血[13]m[12 8[1000]mss 0 [0000](miss) tag data y ta data 1 1 [9]m[8] 1 0 [1]m[0] 1[13]m[12] 11[13]m[12
19 Direct-mapped cache simulation P493 1 0 m[1] m[0] v tag data 1 1 m[13] m[12] 0 [0000] (miss) (4) 1 1 m[9] m[8] v tag data 1 1 m[13] m[12] 8 [1000] (miss) (3) 1 0 m[1] m[0] v tag data 1 1 m[13] m[12] 13 [1101] (miss) (2) 1 0 m[1] m[0] v tag data 0 [0000] (miss) (1) M=16 byte addresses, B=2 bytes/block, S=4 sets, E=1 entry/set Address trace (reads): x 0 [0000] 1 [0001] 13 [1101] 8 [1000] 0 [0000] t=1 s=2 b=1 xx x