P relined Implementation Part ll
Pipelined Implementation Part II
Overview Make the pipelined processor work! Data Hazards a Instruction having register R as source follows shortly after instruction having register R as destination a Common condition, don't want to slow down pipeline Control Hazards a Mispredict conditional branch o Our design predicts all branches as being taken o Naive pipeline executes two extra instructions a Getting return address for ret instruction O PIPE-executes three extra instructions Making Sure It Really Works a What if multiple special cases happen simultaneously? Processor
– 2 – Processor Overview Make the pipelined processor work! Data Hazards ◼ Instruction having register R as source follows shortly after instruction having register R as destination ◼ Common condition, don’t want to slow down pipeline Control Hazards ◼ Mispredict conditional branch ⚫ Our design predicts all branches as being taken ⚫ Naïve pipeline executes two extra instructions ◼ Getting return address for ret instruction ⚫ PIPE- executes three extra instructions Making Sure It Really Works ◼ What if multiple special cases happen simultaneously?
Suggested Reading Chap 4.5 Processor
– 3 – Processor Suggested Reading - Chap 4.5
Branch Misprediction Example demo-3y 0x000: xox1号eax,8eax 0x002: 刀】 ne七 i Not taken 0x007: irm。v1$1,8eax Fall through 0x00d: nop 0x00e: nop 0x00f: nop 0x010: ha七 0x011: t: irmovI $3, edx Target (Should not execute 0x017: 工mov14,岩ecx i Should not execute 0x01a: irmovl $5, edx i Should not execute a Should only execute first 7 instructions Processor
– 4 – Processor Branch Misprediction Example ◼ Should only execute first 7 instructions 0x000: xorl %eax,%eax 0x002: jne t # Not taken 0x007: irmovl $1, %eax # Fall through 0x00d: nop 0x00e: nop 0x00f: nop 0x010: halt 0x011: t: irmovl $3, %edx # Target (Should not execute) 0x017: irmovl $4, %ecx # Should not execute 0x01d: irmovl $5, %edx # Should not execute demo-j.ys
Branch Misprediction Trace #f demo-1 2 34567 0300039268,9 eax FDEMw 0x002: Gne t Not taken FDEM W 0x01l: t: irmovl $3, edx Target FDEM 0x017: irmovl $4, %ecx Target+1 FDEMIW 0x007 irmovl $l, eax Fall Through FDEMWI Cycle 5 M a Incorrectly execute two M Bch=0 instructions at branch target M valA= 0x007 vaE←3 dstE=号edx D vaIC 4 dstE= ecx 5 rB←各eax Processor
– 5 – Processor Branch Misprediction Trace 0x000: xorl %eax,%eax 1 2 3 4 5 6 7 8 9 F D E M 0x002: jne t # Not taken F D E M W W 0x011: t: irmovl $3, %edx # Target F D E M W 0x017: irmovl $4, %ecx # Target+1 F D E M W 0x007: irmovl $1, %eax # Fall Through F D E M W # demo-j F D E M W Cycle 5 E valE 3 dstE = %edx E valE 3 dstE = %edx M M_Bch = 0 M_valA = 0x007 D valC = 4 dstE = %ecx D valC = 4 dstE = %ecx F valC 1 rB %eax F valC 1 rB %eax ◼ Incorrectly execute two instructions at branch target