Cache Memory
1 Cache Memory
Outline General concepts 3 ways to organize cache memory Issues with writes Write cache friendly codes Cache mountain Suggested Reading: 6.4, 6.5, 6.6
2 Outline • General concepts • 3 ways to organize cache memory • Issues with writes • Write cache friendly codes • Cache mountain • Suggested Reading: 6.4, 6.5, 6.6
6.4 Cache Memories
3 6.4 Cache Memories
Cache Memory History At very beginning 3 levels Registers, main memory, disk storage 10 years later, 4 levels Register, SRAM cache, main DRAM memory, disk storage Modern processor, 4-5 levels Registers, SRAM L1, L2(, L3)cache, main DRAM memory, disk storage Cache memories are small fast SRAM-based memories are managed by hardware automatically can be on-chip, on-die, off-chi
4 Cache Memory • History – At very beginning, 3 levels • Registers, main memory, disk storage – 10 years later, 4 levels • Register, SRAM cache, main DRAM memory, disk storage – Modern processor, 4~5 levels • Registers, SRAM L1, L2(,L3) cache, main DRAM memory, disk storage – Cache memories • are small, fast SRAM-based memories • are managed by hardware automatically • can be on-chip, on-die, off-chip
Cache Memory Figure 6.24 P488 CPU chip register Tile L1 ALU cache 三 cache bus system bus memory bus main L2 cache bus interface bridge memory
5 Cache Memory Figure 6.24 P488 main memory I/O bridge L2 cache bus interface ALU register file CPU chip cache bus system bus memory bus L1 cache