Cache Memory Derived quantities Parameters Descriptions M=2m Maximum number of unique memory address S=log 2 (s) Number of set index bits b=log2 ( B) Number of block offset bits t=m-(s+b)Number of tag bits C=BxE xs Cache size(bytes)not including overhead such as the valid and tag bits
11 Cache Memory Derived quantities Parameters Descriptions M=2m s=log2(S) b=log2(B) t=m-(s+b) C=BE S Maximum number of unique memory address Number of set index bits Number of block offset bits Number of tag bits Cache size (bytes) not including overhead such as the valid and tag bits
6.4.2 Direct-mapped cache Figure 6.27 P490 Simplest kind of cache Characterized by exactly one line per set set 0: valid tag cache block E=1 lines per set set 1: valida cache block set S-1: alid tag cache block 12
12 6.4.2 Direct-mapped cache Figure 6.27 P490 • Simplest kind of cache • Characterized by exactly one line per set. valid valid valid tag tag tag • • • set 0: set 1: set S-1: cache block E=1 lines per set cache block cache block
Accessing direct-mapped caches Figure 6.28 P491 Set selection Use the set index bits to determine the set of interest set 0: Valid tag cache block selected set set 1: Valid tag cache block t bits s bits b bits cache block 00001 set S-1: Valid tag m-1 tag set index block offset
13 Accessing direct-mapped caches Figure 6.28 P491 • Set selection – Use the set index bits to determine the set of interest valid valid valid tag tag tag • • • set 0: set 1: set S-1: t bits s bits 0 0 0 0 1 m-1 0 b bits tag set index block offset selected set cache block cache block cache block
Accessing direct-mapped caches Line matching and word extraction find a valid line in the selected set with a matchin tag(line matching) then extract the word (word selection
14 Accessing direct-mapped caches • Line matching and word extraction – find a valid line in the selected set with a matching tag (line matching) – then extract the word (word selection)
Accessing direct-mapped caches Figure 6.29 P491 =1?(1) The valid bit must be set 0 3 5 6 7 selected set (: 0110 Wo W W2 W3 (2 The tag bits in the cache=? line must match the (3)If (1)and (2), then tag bits in the address cache hit and block offset selects t bits s bits b bits starting byte 0110 100 tag set index block offset 15
15 Accessing direct-mapped caches Figure 6.29 P491 1 t bits s bits 0110 i 100 m-1 0 b bits tag set index block offset selected set (i): =1? = ? (3) If (1) and (2), then cache hit, and block offset selects starting byte. (1) The valid bit must be set (2) The tag bits in the cache line must match the tag bits in the address 0110 w0 w1 w2 w3 0 1 2 3 4 5 6 7