Introduction 1394 Open Host Controller Interface Specification Release 1.1 Printed 1/10/00 Upper Address Space is from 48'hFFFF_0000_0000 to 48'hFFFF_EFFF_FFFF.Packets with destination offsets within this range are not candidates for handling by the Physical Request/Response units,and are instead passed to software for processing.The Host Controller shall respond to write requests to this range with an ack_pending,and software should issue a write response with resp_complete only after the data has been written to its specified destination.This range is best suited to protocols that do not tolerate lost packets. CSR Space is from 48'hFFFF_F000_0000 to 48'FFFF_FFFF_FFFF providing a range of 256MB.This range is the reserved register space as specified in ISO/IEC 13213:1994.Most packets with destination offsets within this range are not candidates for handling by the Physical Request/Response units,and are instead passed to software for processing. Some however are handled directly by the Host Controller without involving software and are listed in section 12. 1.6 System Requirements This Host Controller specification is intended to be largely independent of the type of system to which it is attached.The intent is that Host Controller designs that follow this specification may be built for many different types of systems and still adhere to the same programming model.The required system facilities are: a)Host Controller shall be able to initiate accesses of host system memory, b)Host Controller shall be able to modify system memory with byte granularity, c) Host Controller shall be able to signal an exception/interrupt to the host CPU, d) access of 32-bit entities in either system memory or on the Host Controller shall be endian neutral and atomic.No 8-bit or 16-bit access to Host Controller registers are supported. The 1394 Open HCI does not preclude a system from having multiple 1394 Open HCI controllers. 1.7 Alignment 1.7.1 Data alignment The 1394 Open HCI shall perform these two alignment functions: a)Translate between the byte alignments of the host-based data and the quadlet aligned FIFO.For instance,if a 5 byte 1394 data packet is to be stored at host bus address 6,then the first two bytes of the first data quadlet in the FIFO shall be stored at host bus address 6 and 7 using a single quadlet write,then the next two bytes of the first quadlet in the FIFO combined with the first byte of the next quadlet in the FIFO are written to host bus address 8, 9.and10. b)Stuff extra zero bytes into the transmit FIFO when the number of bytes to transmit is not an integral number of quadlets. 1.7.2 Memory structure and buffer alignment Alignment requirements for host memory data structures and host memory buffers can be found in sections of this document where those elements are described. Page 10 Copyright 1996-2000 All rights reserved
Page 10 Copyright © 1996-2000 All rights reserved. Introduction 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 Upper Address Space is from 48’hFFFF_0000_0000 to 48’hFFFF_EFFF_FFFF. Packets with destination offsets within this range are not candidates for handling by the Physical Request/Response units, and are instead passed to software for processing. The Host Controller shall respond to write requests to this range with an ack_pending, and software should issue a write response with resp_complete only after the data has been written to its specified destination. This range is best suited to protocols that do not tolerate lost packets. CSR Space is from 48’hFFFF_F000_0000 to 48’FFFF_FFFF_FFFF providing a range of 256MB. This range is the reserved register space as specified in ISO/IEC 13213:1994. Most packets with destination offsets within this range are not candidates for handling by the Physical Request/Response units, and are instead passed to software for processing. Some however are handled directly by the Host Controller without involving software and are listed in section 12. 1.6 System Requirements This Host Controller specification is intended to be largely independent of the type of system to which it is attached. The intent is that Host Controller designs that follow this specification may be built for many different types of systems and still adhere to the same programming model. The required system facilities are: a) Host Controller shall be able to initiate accesses of host system memory, b) Host Controller shall be able to modify system memory with byte granularity, c) Host Controller shall be able to signal an exception/interrupt to the host CPU, d) access of 32-bit entities in either system memory or on the Host Controller shall be endian neutral and atomic. No 8-bit or 16-bit access to Host Controller registers are supported. The 1394 Open HCI does not preclude a system from having multiple 1394 Open HCI controllers. 1.7 Alignment 1.7.1 Data alignment The 1394 Open HCI shall perform these two alignment functions: a) Translate between the byte alignments of the host-based data and the quadlet aligned FIFO. For instance, if a 5 byte 1394 data packet is to be stored at host bus address 6, then the first two bytes of the first data quadlet in the FIFO shall be stored at host bus address 6 and 7 using a single quadlet write, then the next two bytes of the first quadlet in the FIFO combined with the first byte of the next quadlet in the FIFO are written to host bus address 8, 9, and 10. b) Stuff extra zero bytes into the transmit FIFO when the number of bytes to transmit is not an integral number of quadlets. 1.7.2 Memory structure and buffer alignment Alignment requirements for host memory data structures and host memory buffers can be found in sections of this document where those elements are described
Conventions-Notation and Terms1394 Open Host Controller Interface Specification/Release 1.1 Printed 1/10/00 2.Conventions-Notation and Terms 2.1 Notation 2.1.1 Conformance glossary Several keywords are used to differentiate between different levels of requirements and optionality,as defined below. These key words shall take the following definitions for normative sections of this specifications. expected:A keyword used to describe the behavior of the hardware or software in the design models assumed by this standard.Other hardware and software design models may also be implemented. ignored:A keyword that describes bits,bytes,quadlets,octlets or fields whose values are not checked by the recipient. may:A keyword that indicates flexibility of choice with no implied preference. shall:A keyword indicating a mandatory requirement.Designers are required to implement all such mandatory require- ments to ensure interoperability with other products conforming to this standard. should:A keyword indicating flexibility of choice with a strongly preferred alternative.Equivalent to the phrase "is recommended." undefined:A keyword that defines the condition of a bit which software shall take no action on (whether it be zero or one).If software requires a specific action for the bit definition,then software shall initialize the bit. 2.1.2 Numeric Notation Unless otherwise specified,numbers will be represented in Verilog language style.In particular,numbers with a"h" prefix are hexadecimal,"b"are binary,and"d"or those without a prefix are decimal.If a number precedes the"" then it indicates the length of the number in bits.For example,4'h8 is the binary number'b1000. 2.1.3 Bit Notation So that the size and location of fields can be better understood,the bits within quadlet registers are labeled,where bit 31 corresponds to the most-significant bit and bit 0 corresponds to the least-significant bit.They do not correspond to the transmission order on the 1394 bus. All registers and data structures in this document have the most significant bit(msb-bit 31)shown on the far left. 2.1.4 Register Notation There are two types of registers described in this document;read/write registers and set and clear registers.The notation used for each is described below,as well as notation used for register reset values and reserved fields and registers. Copyright 1996-2000 All rights reserved. Page 11
Copyright © 1996-2000 All rights reserved. Page 11 Conventions - Notation and Terms1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 2. Conventions - Notation and Terms 2.1 Notation 2.1.1 Conformance glossary Several keywords are used to differentiate between different levels of requirements and optionality, as defined below. These key words shall take the following definitions for normative sections of this specifications. expected: A keyword used to describe the behavior of the hardware or software in the design models assumed by this standard. Other hardware and software design models may also be implemented. ignored: A keyword that describes bits, bytes, quadlets, octlets or fields whose values are not checked by the recipient. may: A keyword that indicates flexibility of choice with no implied preference. shall: A keyword indicating a mandatory requirement. Designers are required to implement all such mandatory requirements to ensure interoperability with other products conforming to this standard. should: A keyword indicating flexibility of choice with a strongly preferred alternative. Equivalent to the phrase “is recommended.” undefined: A keyword that defines the condition of a bit which software shall take no action on (whether it be zero or one). If software requires a specific action for the bit definition, then software shall initialize the bit. 2.1.2 Numeric Notation Unless otherwise specified, numbers will be represented in Verilog language style. In particular, numbers with a “’h” prefix are hexadecimal, “’b” are binary, and “’d” or those without a prefix are decimal. If a number precedes the “ ’ ”, then it indicates the length of the number in bits. For example, 4’h8 is the binary number ’b1000. 2.1.3 Bit Notation So that the size and location of fields can be better understood, the bits within quadlet registers are labeled, where bit 31 corresponds to the most-significant bit and bit 0 corresponds to the least-significant bit. They do not correspond to the transmission order on the 1394 bus. All registers and data structures in this document have the most significant bit (msb - bit 31) shown on the far left. 2.1.4 Register Notation There are two types of registers described in this document; read/write registers and set and clear registers. The notation used for each is described below, as well as notation used for register reset values and reserved fields and registers
Conventions-Notation and Terms1394 Open Host Controller Interface Specification/Release 1.1 Printed 1/10/00 2.1.4.1 Read/Write registers Read/write registers are registers for which a single address is defined and for which fields may be defined with one or more of the following attributes: Table 2-1-read/write register field access tags access tag (rwu) name meaning read field may be read write field may be written from the host bus u update field may be autonomously updated by Open HCI hardware 2.1.4.2 Set and Clear registers Throughout this document there are Host Controller registers that are identified as Set and Clear registers.These registers have the property of having two addresses by which they may be referenced by the host.Unless otherwise stated in the description of the register,a host read of either address will return the current contents of the register.Host writes, however,have different effects when addressing the different addresses. When the host writes to the Set address the value written is taken as a bit mask indicating which bits in the underlying register are to be set to one.A one bit in the value written indicates that the corresponding bit in the register is to be set to one,while a zero bit in the value written indicates that the corresponding bit in the register is not to be changed.Simi- larly,host writes to the Clear address specify a value that is a bit mask of bits to clear to zero in the underlying register, a one bit means to clear the corresponding bit while a zero bit means to leave the corresponding bit unchanged.It is intended that writing zero bits to these addresses has no effect on the corresponding bits in the underlying register, including transient effects that could affect the operation of the Host Controller. There are several reasons to use this type of register: The host doesn't need to do both a read and a write to affect only a single bit. The host doesn't risk the Host Controller modifying a bit while the host does a read-modify-write operation,thus causing unintended effects. The host doesn't have to serialize its access to frequently used registers in order to ensure that conflict with another process doesn't cause unintended effects. For set and clear registers that have an undefined value following a reset,it is recommended that software write all ones to the Clear address to ensure the register has a known value. Table 2-2-Set and Clear register field access tags access tag (rscu) name meaning read field may be read set field may be set from the host bus clear field may be cleared from the host bus update field may be autonomously updated by Open HCI hardware Page 12 Copyright 1996-2000 All rights reserved
Page 12 Copyright © 1996-2000 All rights reserved. Conventions - Notation and Terms1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 2.1.4.1 Read/Write registers Read/write registers are registers for which a single address is defined and for which fields may be defined with one or more of the following attributes: 2.1.4.2 Set and Clear registers Throughout this document there are Host Controller registers that are identified as Set and Clear registers. These registers have the property of having two addresses by which they may be referenced by the host. Unless otherwise stated in the description of the register, a host read of either address will return the current contents of the register. Host writes, however, have different effects when addressing the different addresses. When the host writes to the Set address the value written is taken as a bit mask indicating which bits in the underlying register are to be set to one. A one bit in the value written indicates that the corresponding bit in the register is to be set to one, while a zero bit in the value written indicates that the corresponding bit in the register is not to be changed. Similarly, host writes to the Clear address specify a value that is a bit mask of bits to clear to zero in the underlying register, a one bit means to clear the corresponding bit while a zero bit means to leave the corresponding bit unchanged. It is intended that writing zero bits to these addresses has no effect on the corresponding bits in the underlying register, including transient effects that could affect the operation of the Host Controller. There are several reasons to use this type of register: • The host doesn’t need to do both a read and a write to affect only a single bit. • The host doesn’t risk the Host Controller modifying a bit while the host does a read-modify-write operation, thus causing unintended effects. • The host doesn’t have to serialize its access to frequently used registers in order to ensure that conflict with another process doesn’t cause unintended effects. For set and clear registers that have an undefined value following a reset, it is recommended that software write all ones to the Clear address to ensure the register has a known value. Table 2-1 — read/write register field access tags access tag (rwu) name meaning r read field may be read w write field may be written from the host bus u update field may be autonomously updated by Open HCI hardware Table 2-2 — Set and Clear register field access tags access tag (rscu) name meaning r read field may be read s set field may be set from the host bus c clear field may be cleared from the host bus u update field may be autonomously updated by Open HCI hardware
Conventions-Notation and Terms1394 Open Host Controller Interface Specification/Release 1.1 Printed 1/10/00 2.1.4.3 Register Reset Values Register field descriptions may be tagged with one or more of the following reset values.This column indicates the value of the field immediately following a soft reset or hardware reset.Except where otherwise noted,the results from a soft reset and hardware reset are the same.Note that the reset column is for software and hardware resets only and does not include bus reset values (those are discussed as needed in the applicable text). Table 2-3-Register field reset values reset value meaning x'by or x'hy Indicates the value (in binary or hexadecimal)of the field upon completion of a reset.For description of Verilog notation see section 2.1.2. undef Following a reset,the value of this field is undefined and may contain(any combination of)zero(s)or one(s).Software shall initialize bits that reset to"undef before it uses them. N/A Not applicable.A reset does not have any effect on this field. Unless otherwise specified,all fields will remain unchanged after a 1394 bus reset. 2.1.4.4 Reserved fields All reserved fields(indicated by a hatched or grayed-out pattern)are read as zeros,shall be ignored by software,and shall be written as zeros. 2.1.4.5 Reserved registers Addresses within the host bus Open HCI Register Address space that are marked as reserved shall return zeros when read and shall ignore the write data value. 2.1.4.6 Register field notation In descriptions which refer to specific register fields,the notation Rrrrr.f will be used where Rrrrr refers to the register name and frefers to the referenced field within that register. Copyright 1996-2000 All rights reserved. Page 13
Copyright © 1996-2000 All rights reserved. Page 13 Conventions - Notation and Terms1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 2.1.4.3 Register Reset Values Register field descriptions may be tagged with one or more of the following reset values. This column indicates the value of the field immediately following a soft reset or hardware reset. Except where otherwise noted, the results from a soft reset and hardware reset are the same. Note that the reset column is for software and hardware resets only and does not include bus reset values (those are discussed as needed in the applicable text). Unless otherwise specified, all fields will remain unchanged after a 1394 bus reset. 2.1.4.4 Reserved fields All reserved fields (indicated by a hatched or grayed-out pattern) are read as zeros, shall be ignored by software, and shall be written as zeros. 2.1.4.5 Reserved registers Addresses within the host bus Open HCI Register Address space that are marked as reserved shall return zeros when read and shall ignore the write data value. 2.1.4.6 Register field notation In descriptions which refer to specific register fields, the notation Rrrrr.fffff will be used where Rrrrr refers to the register name and fffff refers to the referenced field within that register. Table 2-3 — Register field reset values reset value meaning x’by or x’hy Indicates the value (in binary or hexadecimal) of the field upon completion of a reset. For description of Verilog notation see section 2.1.2. undef Following a reset, the value of this field is undefined and may contain (any combination of) zero(s) or one(s). Software shall initialize bits that reset to “undef” before it uses them. N/A Not applicable. A reset does not have any effect on this field
Conventions-Notation and Terms1394 Open Host Controller Interface Specification/Release 1.1 Printed 1/10/00 2.2 Terms The following terms and acronyms are used throughout this document. ack_busy* Any of the "busy"acknowledgments:ack_busy_X,ack_busy_A,ack_busy_B. AR DMA Asynchronous Receive DMA AR DMA Request Refers to the asynchronous receive DMA context that handles all incoming request packets not handled by the physical request unit AR DMA Response Refers to the asynchronous receive DMA context that handles all incoming response packets. asynchronous stream A stream packet for which only a channel has been reserved at the isochronous resource manager. packet An asynchronous stream packet shall be transmitted during the asynchronous period and not during the isochronous period.For the same channel number,there is no restriction on multiple talkers nor upon a single talker sending multiple asynchronous stream packets.Fair arbitration rules govern the transmission of these packets.See also isochronous stream packet and stream packet. AT DMA Asynchronous Transmit DMA AT DMA Request Unit Refers to the asynchronous transmit DMA subunit which moves transmit packets from buffers in memory to the request transmit FIFO. AT DMA Response Unit Refers to the asynchronous transmit DMA subunit which moves transmit packets from buffers in memory to the response transmit FIFO. back-out A process by which a flawed received packet that has been placed in a set of received buffers is removed.The Open HCI backs-out a packet by ensuring that reported buffer space availability does not reflect flawed packet reception big endian A term used to describe the arithmetic significance of data bytes within a multiple data-byte value;the data byte with the largest address is the least significant. bridge A hardware adapter that forwards transactions between buses.a buffer-fill mode A receive mode in which packet data is concatenated into receive buffers channel Refers to an isochronous channel number. CSR architecture ISO/IEC 13213:1994 [ANSI/IEEE Std 1212,1994 Edition],Information technology-Micropro- cessor systems-Control and Status Registers (CSR)Architecture for microcomputer buses.The CSR architecture supports the concept of bus bridges,which can transparently forward transac- tions from one compliant bus to another. config ROM A portion of a node's 1394 address space defined by clause 8 of ISO/IEC 13213:1994 [ANSI/IEEE Std 1212,1994 Edition].The region contains information describing the node and its units.The region is read-only to other 1394 nodes.See also GUID ROM and PCI Expansion ROM. DMA context A distinct logical stream(not necessarily physical)through the Open HCI which can be described by a DMA context program and a minimum of two registers:ContextControl and CommandPtr. DMA context program A list of DMA descriptors which identify buffers used for data transfer. DMA controller Refers to the mechanism used in support of a specific DMA function.Each controller utilizes and maintains its own set of registers to perform its specified functionality. DMA descriptor A data structure used to describe buffers and buffer-list control. DMA descriptor block A group of DMA descriptors that are contiguous in host memory and can therefore be prefetched by the Host Controller.The last DMA descriptor in a block contains the address of the next block as well as a count of the number of descriptors contained in the next block.This count is referred to as the Z value dual-buffer-mode An isochronous receive mode in which a packet is divided into two portions each concatenated into independent sets of receive buffers Page 14 Copyright 1996-2000 All rights reserved
Page 14 Copyright © 1996-2000 All rights reserved. Conventions - Notation and Terms1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 2.2 Terms The following terms and acronyms are used throughout this document. ack_busy* Any of the “busy” acknowledgments: ack_busy_X, ack_busy_A, ack_busy_B. AR DMA Asynchronous Receive DMA. AR DMA Request Refers to the asynchronous receive DMA context that handles all incoming request packets not handled by the physical request unit. AR DMA Response Refers to the asynchronous receive DMA context that handles all incoming response packets. asynchronous stream packet A stream packet for which only a channel has been reserved at the isochronous resource manager. An asynchronous stream packet shall be transmitted during the asynchronous period and not during the isochronous period. For the same channel number, there is no restriction on multiple talkers nor upon a single talker sending multiple asynchronous stream packets. Fair arbitration rules govern the transmission of these packets. See also isochronous stream packet and stream packet. AT DMA Asynchronous Transmit DMA. AT DMA Request Unit Refers to the asynchronous transmit DMA subunit which moves transmit packets from buffers in memory to the request transmit FIFO. AT DMA Response Unit Refers to the asynchronous transmit DMA subunit which moves transmit packets from buffers in memory to the response transmit FIFO. back-out A process by which a flawed received packet that has been placed in a set of received buffers is removed. The Open HCI backs-out a packet by ensuring that reported buffer space availability does not reflect flawed packet reception. big endian A term used to describe the arithmetic significance of data bytes within a multiple data-byte value; the data byte with the largest address is the least significant. bridge A hardware adapter that forwards transactions between buses.a buffer-fill mode A receive mode in which packet data is concatenated into receive buffers channel Refers to an isochronous channel number. CSR architecture ISO/IEC 13213: 1994 [ANSI/IEEE Std 1212, 1994 Edition], Information technology - Microprocessor systems - Control and Status Registers (CSR) Architecture for microcomputer buses. The CSR architecture supports the concept of bus bridges, which can transparently forward transactions from one compliant bus to another. config ROM A portion of a node’s 1394 address space defined by clause 8 of ISO/IEC 13213:1994 [ANSI/IEEE Std 1212, 1994 Edition]. The region contains information describing the node and its units. The region is read-only to other 1394 nodes. See also GUID ROM and PCI Expansion ROM. DMA context A distinct logical stream (not necessarily physical) through the Open HCI which can be described by a DMA context program and a minimum of two registers: ContextControl and CommandPtr. DMA context program A list of DMA descriptors which identify buffers used for data transfer. DMA controller Refers to the mechanism used in support of a specific DMA function. Each controller utilizes and maintains its own set of registers to perform its specified functionality. DMA descriptor A data structure used to describe buffers and buffer-list control. DMA descriptor block A group of DMA descriptors that are contiguous in host memory and can therefore be prefetched by the Host Controller. The last DMA descriptor in a block contains the address of the next block as well as a count of the number of descriptors contained in the next block. This count is referred to as the Z value. dual-buffer-mode An isochronous receive mode in which a packet is divided into two portions each concatenated into independent sets of receive buffers