Generic port declarations a Generic Declarations ☆用于将参数传入 Entity。例如:数据线宽度,器件的延时参数、负载电容电阻、 驱动能力、功耗等等。 u Port Declarations: port name: <mode>: <typex 令<mode>:管脚的模式 In(输入) Out(输出) Buffer(输出带内部反馈) nout(双向) ☆<Ipe>:数据类型 Boolean: False. True Bit:0.1 Std logic:X2,0°,1,Z,-,W,L,H,支持多信号判决 Std ulogic:与 Std logic类型一样,不支持多信号判决 Bit vector std logic vector - Integer Natural Positive Real. time 自定义数据类型:如数组等
Generic & Port Declarations ❑ Generic Declarations ❖ 用于将参数传入Entity。例如：数据线宽度，器件的延时参数、负载电容电阻、 驱动能力、功耗等等。 ❑ Port Declarations： port_name: <mode> : <type> ❖ <mode>：管脚的模式 – In (输入) － Out (输出) – Buffer (输出带内部反馈) － Inout (双向) ❖ <Type>: 数据类型 – Boolean: False, True – Bit: ’0’, ‘1’ – Std_logic: ‘X’, ‘0’, ‘1’, ‘Z’, ‘-’, ‘W’, ‘L’, ‘H’，支持多信号判决 – Std_ulogic: 与Std_logic类型一样，不支持多信号判决 – Bit_vector & std_logic_vector: – Integer: • Natural • Positive – Real: time – 自定义数据类型：如数组等
Architecture(结构体) 口描述设计的功能或者结构 口必须与某个 entity相联系 口一个 entity可以对应多个 architecture编译时通过 configuration来指定) 口 Architecture中的各个语句是并发执行的,对应于电路硬 件中的不同部件 口 Architecture的描述风格 ◇行为描述—描述实体的功能,RTL级 算法描述 数据流描述 令结构描述——描述实体的结构,门级 ◇混合描述
Architecture（结构体） ❑ 描述设计的功能或者结构 ❑ 必须与某个entity相联系 ❑ 一个entity可以对应多个architecture(编译时通过 configuration来指定) ❑ Architecture中的各个语句是并发执行的，对应于电路硬 件中的不同部件 ❑ Architecture的描述风格 ❖ 行为描述——描述实体的功能，RTL级 – 算法描述 – 数据流描述 ❖ 结构描述——描述实体的结构，门级 ❖ 混合描述
Architecture组成 口 Architecture定义 ARCHITECTURE arch name Of entity name IS signal declarations constant declarations type subtype declarations; component declarations subprogram declarations BEGIN Process Statements Concurrent Procedure Calls Concurrent Signal Assignment Conditional Signal Assignment; Selected Signal Assignment Component Instantiation Statements Generate statements END arch name
Architecture组成 ❑ Architecture定义 ARCHITECTURE arch_name OF entity_name IS signal declarations; constant declarations; type & subtype declarations; component declarations; subprogram declarations; BEGIN Process Statements; Concurrent Procedure Calls; Concurrent Signal Assignment; Conditional Signal Assignment; Selected Signal Assignment; Component Instantiation Statements; Generate Statements; END arch_name;
结构描述例子半加器 Architecture struct ha of half adder is component and gate port( al, a2: in std logic 13: out std logic); AND2 end component; a□ OUTPUT C component xor gate rt( al, a2: in std le a3: out std logic); XOR end component OUTPUT Begin b gl: and gate port map(a, b, 2: xor gate port map(a, b, s) End struct ha
结构描述例子——半加器 Architecture struct_ha of half_adder is component and_gate port( a1,a2: in std_logic; a3: out std_logic); end component; component xor_gate port( a1,a2: in std_logic; a3: out std_logic); end component; Begin g1: and_gate port map(a,b,c); g2: xor_gate port map(a,b,s); End struct_ha;
行为描述例子半加器 口算法描述 口数据流描述 Architecture behave ha of half adder is Architecture behave ha of half adder Beg gl: process(a, b) c<=a and b S<=axor b: if a=1 and b=1 then End struct ha end if; end process, g2: process(a, b) if a=l' and b=40 then elsif a=0 and b= 1 nd if. end process End struct ha
行为描述例子——半加器 ❑ 算法描述 Architecture behave_ha of half_adder is Begin g1: process(a,b) begin if a=‘1’ and b=‘1’ then c<=‘1’; else c<=‘0’; end if; end process; g2: process(a,b) begin if a=‘1’ and b=‘0’ then c<=‘1’; elsif a=‘0’ and b=‘1’ c<=‘1’; else c<=‘0’; end if; end process; End struct_ha; ❑ 数据流描述 Architecture behave_ha of half_adder is Begin c<= a and b; s<=a xor b; End struct_ha;