INTEGRATED CIRCUITS DATA SHEET PDIUSBD12 USB interface device with parallel bus Product specification 1999Jan08 Supersedes data of 1998 Sep 24 Philips Semiconductors E PHILIPS
PDIUSBD12 USB interface device with parallel bus Product specification Supersedes data of 1998 Sep 24 1999 Jan 08 INTEGRATED CIRCUITS
Philips semiconductors Product specification USB interface device with parallel bus PDIUSBD12 FEATURES DE SCRIPTION The PDIUSBD12 is a cost and feature-optimized USB device. It normally used in microcontroller-based systems and communicates High performance USB interface device with integrated SIE, with the system microcontroller over the high speed FIFO memory, transceiver and voltage regulator general-purpose parallel interface. It also supports local DMA Compliant with most Device Class specifications transfer High-speed (2 Mbytes) parallel interface to any external This modular approach to implementing a USB interface allows the designer to choose the optimum system microcontroller from the available wide variety. This flexibility cuts down the development e Fully autonomous DMA operation time, risks, and costs by allowing the use of the existing architecture and minimize firmware investments This results the fastest way e Integrated 320 bytes of multi-configuration FIFO memory to develop the most cost-effective USB peripheral solution Double buffering scheme for main endpoint increases throughput The PDIUSBD 12 fully conforms to the USB specification Rev. 1.1 and eases real time data transfer it is also designed to be compliant with most device class 1MByte/s data transfer rate achievable in Bulk mode, 1Mbit/s data specifications: Imaging Class, Mass Storage Devices, transfer rate achievable in isochronous mode Communication Devices, Printing Devices, and Human Interface Devices. As such, the PDIUSBD12 is ideally suited for many peripherals like Printer, Scanner, External Mass Storage(Zip Drive). Digital Still Camera, etc. It offers an immediate cost reduction for Controllable Lazy Clock output during suspend applications that currently use SCSI implementations Software controllable connection to the USB bus( SoftConnectTM The PDIUSBD12 low suspend power consumption along with the Good USB connection indicator that blinks with traffic Lazy clock output allows for easy implementation of equipment that is compliant to the ACPl, OnNOW, and USB power management requirements. The low operating power allows the implementation of Programmable clock frequency output bus-powered peripherals Complies with the ACPL, OnNOW, and USB power management requirements ble quency cryst oscillator, and integration of termination features contribute to significant cost savings in the system 0 Available in So28 and TSSOP28 pin packages implementation and at the same time ease the implementation of advanced USB functionality into the peripherals ● Full industrial grade operation from-40to+85°C Higher than 8kV in-circuit ESD protection lowers cost of extra Full-scan design with high fault coverage(99%)ensures high e Operation with dual voltages: 3.3+0.3v or extended 5V supply range of 3.6-5.5V e Multiple interrupt modes to facilitate both bulk and isochronous transfers ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICANORTH AMERICAPKGDWG# 28-pin plastic so 40°cto+85°C PDIUSBD12 D PDIUSBD12 D sOT136-1 28-pin plastic TSSOP -40°cto+85°C PDIUSBD12 PW PDUSBD12PWDHSOT361-1 1999Jan08 853-211020620
Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 2 853–2110 20620 FEATURES • Complies with the Universal Serial Bus specification Rev. 1.1 • High performance USB interface device with integrated SIE, FIFO memory, transceiver and voltage regulator • Compliant with most Device Class specifications • High-speed (2 Mbytes/s) parallel interface to any external microcontroller/microprocessor • Fully autonomous DMA operation • Integrated 320 bytes of multi-configuration FIFO memory • Double buffering scheme for main endpoint increases throughput and eases real time data transfer • 1MByte/s data transfer rate achievable in Bulk mode, 1Mbit/s data transfer rate achievable in Isochronous mode • Bus-powered capability with very good EMI performance • Controllable LazyClock output during suspend • Software controllable connection to the USB bus (SoftConnect) • Good USB connection indicator that blinks with traffic (GoodLink) • Programmable clock frequency output • Complies with the ACPI, OnNOW, and USB power management requirements • Internal power-on reset and low voltage reset circuit • Available in SO28 and TSSOP28 pin packages • Full industrial grade operation from –40 to +85°C • Higher than 8kV in-circuit ESD protection lowers cost of extra components • Full-scan design with high fault coverage (>99%) ensures high quality • Operation with dual voltages: 3.3 ± 0.3V or extended 5V supply range of 3.6 – 5.5V • Multiple interrupt modes to facilitate both bulk and isochronous transfers DESCRIPTION The PDIUSBD12 is a cost and feature-optimized USB device. It is normally used in microcontroller-based systems and communicates with the system microcontroller over the high speed general-purpose parallel interface. It also supports local DMA transfer. This modular approach to implementing a USB interface allows the designer to choose the optimum system microcontroller from the available wide variety. This flexibility cuts down the development time, risks, and costs by allowing the use of the existing architecture and minimize firmware investments. This results in the fastest way to develop the most cost-effective USB peripheral solution. The PDIUSBD12 fully conforms to the USB specification Rev. 1.1. It is also designed to be compliant with most device class specifications: Imaging Class, Mass Storage Devices, Communication Devices, Printing Devices, and Human Interface Devices. As such, the PDIUSBD12 is ideally suited for many peripherals like Printer, Scanner, External Mass Storage (Zip Drive), Digital Still Camera, etc. It offers an immediate cost reduction for applications that currently use SCSI implementations. The PDIUSBD12 low suspend power consumption along with the LazyClock output allows for easy implementation of equipment that is compliant to the ACPI, OnNOW, and USB power management requirements. The low operating power allows the implementation of bus-powered peripherals. In addition, it also incorporates features like SoftConnect, GoodLink, programmable clock output, low frequency crystal oscillator, and integration of termination resistors. All of these features contribute to significant cost savings in the system implementation and at the same time ease the implementation of advanced USB functionality into the peripherals. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 28-pin plastic SO –40°C to +85°C PDIUSBD12 D PDIUSBD12 D SOT136-1 28-pin plastic TSSOP –40°C to +85°C PDIUSBD12 PW PDUSBD12PW DH SOT361-1
Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 BLOCK DIAGRAM 6 MHz UPSTREAM INTEGRATED BIT CLOCK 1.5k9 ANALOG PHILIPS MEMORY VOLTAGE REGULATOR NOTE. This is a conceptual block diagram and does not include each individual signa Analog Transceiver SoftconnectTw The integrated transceiver interfaces directly to the USB cables The connection to the USB is accomplished by bringing D+(for hrough termination resistors high-speed USB device) high through a 1.5 kQ pull-up resistor. In Voltage Regulator the PDIUSBD12, the 1.5 k@2 pull-up resistor is integrated on-chip and is not connected to Vcc by default. The connection is A 3. 3v regulator is integrated on-chip to supply og established through a command sent by the external/system transceiver. This voltage is also provided as ar connect to microcontroller. This allows the system microcontroller to complete the external 1.5 k]2 pull-up resistor. Altematively, USBD12 its initialization sequence before deciding to establish connection to provides Soft Connectm technology with integrated 1.5 k@2 pull-up the USB. Re-initialization of the usb bus connection can also be performed without requiring to pull out the cable PLL The PDIUSBD12 will check for USB VBUS availability before the A 6 MHz to 48 MHz clock multiplier PLL (Phase-Locked Loop) is connection can be established. VBUS sensing is provided through integrated on-chip. This allows for the use of low-cost 6 MHz crystal EOT N pin. See the pin description for details. Sharing of VBUs EMI is also minimized due to the lower frequency crystal. No sensing and EOT N can be easily accomplished by using VBUS external components are needed for the operation of the PLL. voltage as the pull up voltage for the normally open-drain output of the dma controller pir ecove It should be noted that the tolerance of the intemal resistors is The bit clock recovery circuit recovers the clock from the incomin k ugher(25%)than that specified by the USB specification(5%) USB data stream using 4X over-sampling principle. It is able to track jitter and frequency drift specified by the USB specification. However, the overall VsE voltage specification for the connection can still be met with good margin. The decision to make sure of this Philips Serial Interface Engine(PSI) feature lies with the users he Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention SoftconnectM is a patent pending technology from Philips The functions of this block include: synchronization patten recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation, PID verification/generation, address ecognition, and hands
Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 3 BLOCK DIAGRAM PARALLEL AND DMA INTERFACE ANALOG TX/RX PHILIPS SIE INTEGRATED RAM BIT CLOCK RECOVERY MEMORY MANAGEMENT UNIT 6 MHz D+ D– UPSTREAM PORT PLL SoftConnect D+ 3.3V 1.5k SV00859 VOLTAGE REGULATOR NOTE: * This is a conceptual block diagram and does not include each individual signal. Analog Transceiver The integrated transceiver interfaces directly to the USB cables through termination resistors. Voltage Regulator A 3.3V regulator is integrated on-chip to supply the analog transceiver. This voltage is also provided as an output to connect to the external 1.5 kΩ pull-up resistor. Alternatively, the PDIUSBD12 provides SoftConnect technology with integrated 1.5 kΩ pull-up resistor. PLL A 6 MHz to 48 MHz clock multiplier PLL (Phase-Locked Loop) is integrated on-chip. This allows for the use of low-cost 6 MHz crystal. EMI is also minimized due to the lower frequency crystal. No external components are needed for the operation of the PLL. Bit Clock Recovery The bit clock recovery circuit recovers the clock from the incoming USB data stream using 4X over-sampling principle. It is able to track jitter and frequency drift specified by the USB specification. Philips Serial Interface Engine (PSIE) The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. The functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation, PID verification/generation, address recognition, and handshake evaluation/generation. SoftConnect The connection to the USB is accomplished by bringing D+ (for high-speed USB device) high through a 1.5 kΩ pull-up resistor. In the PDIUSBD12, the 1.5 kΩ pull-up resistor is integrated on-chip and is not connected to VCC by default. The connection is established through a command sent by the external/system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establish connection to the USB. Re-initialization of the USB bus connection can also be performed without requiring to pull out the cable. The PDIUSBD12 will check for USB VBUS availability before the connection can be established. VBUS sensing is provided through EOT_N pin. See the pin description for details. Sharing of VBUS sensing and EOT_N can be easily accomplished by using VBUS voltage as the pull up voltage for the normally open-drain output of the DMA controller pin. It should be noted that the tolerance of the internal resistors is higher (25%) than that specified by the USB specification (5%). However, the overall VSE voltage specification for the connection can still be met with good margin. The decision to make sure of this feature lies with the users. SoftConnect is a patent pending technology from Philips Semiconductors
Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 GoodLinkTM Parallel and DMA Interface Good USB connection indication is provided through GoodLinkTM A generic parallel interface is defined for ease-of-use, speed, and technology. During enumeration, the LED indicator will blink ON allows direct interfacing to major microcontrollers. To a momentarily corresponding to the enumeration traffic. When the microcontroller, the PDIUSBD12 appears as a memory device with PDIUSBD12 is successfully enumerated and configured, the LED 8-bit data bus and 1 address bit(occupying 2 locations). The indicator will be permanently ON. Subsequent successful (with PDIUSBD12 supports both multiplexed and non-multiplexed acknowledgement) transfer to and from the PDIUSBD12 will blink address and data bus. The PDIUSBD12 also supports DMA (Direct OFF the LED During suspend, the LED will be OFF. Memory Access)transfer which allows the main endpoint(endpoint This feature provides a user-friendly indicator on the status of the 2)to directly transfer to and from the local shared memory. Both USB device. the connected hub and the usB traffic. it is a useful single cycle and burst mode DMA transfers are supported field diagnostics tool to isolate faulty equipment. This feature helps Example of parallel interface to a dedicated 80c51 lower field support and hotline costs. In this example, the ALE is permanently tied LOW to signify a emory Management Unit(MMU)and eparate address and data bus configuration. The A0 pin of the Integrated RAM PDIUSBD12 connects to any of the 80C51 WO port. This port The MMU and the integrated RAM buffer the difference in speed controls command or data phase to the PDIUSBD12. The between USB, running in bursts of 12 Mbits/s and the parallel multiplexed address and data bus of the 80C51 can now be connected directly to the data bus of the PDIUSBD 12. The address interface to the microcontroller this allows the microcontroller to read and write USB packets at its own speed phase will simply be ignored by the PDIUSBD12. The crystal input of the 80C51 can be supplied by the CLKoUT output of the PDIUSBD12 80c51 INT N DATA [7: 0 P.70.0yA:0 RD N CLKOUT XTAL1 CS N
Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 4 GoodLink Good USB connection indication is provided through GoodLink technology. During enumeration, the LED indicator will blink ON momentarily corresponding to the enumeration traffic. When the PDIUSBD12 is successfully enumerated and configured, the LED indicator will be permanently ON. Subsequent successful (with acknowledgement) transfer to and from the PDIUSBD12 will blink OFF the LED. During suspend, the LED will be OFF. This feature provides a user-friendly indicator on the status of the USB device, the connected hub and the USB traffic. It is a useful field diagnostics tool to isolate faulty equipment. This feature helps lower field support and hotline costs. Memory Management Unit (MMU) and Integrated RAM The MMU and the integrated RAM buffer the difference in speed between USB, running in bursts of 12 Mbits/s and the parallel interface to the microcontroller. This allows the microcontroller to read and write USB packets at its own speed. Parallel and DMA Interface A generic parallel interface is defined for ease-of-use, speed, and allows direct interfacing to major microcontrollers. To a microcontroller, the PDIUSBD12 appears as a memory device with 8-bit data bus and 1 address bit (occupying 2 locations). The PDIUSBD12 supports both multiplexed and non-multiplexed address and data bus. The PDIUSBD12 also supports DMA (Direct Memory Access) transfer which allows the main endpoint (endpoint 2) to directly transfer to and from the local shared memory. Both single cycle and burst mode DMA transfers are supported. Example of parallel interface to a dedicated 80C51 In this example, the ALE is permanently tied LOW to signify a separate address and data bus configuration. The A0 pin of the PDIUSBD12 connects to any of the 80C51 I/O port. This port controls command or data phase to the PDIUSBD12. The multiplexed address and data bus of the 80C51 can now be connected directly to the data bus of the PDIUSBD12. The address phase will simply be ignored by the PDIUSBD12. The crystal input of the 80C51 can be supplied by the CLKOUT output of the PDIUSBD12. PDIUSBD12 80C51 INT_N A0 DATA [7:0] WR_N RD_N CLKOUT CS_N ALE XTAL1 –RD/P3.7 –WR/P3.6 P [0.7:0.0]/AD [7:0] ANY I/O PORT (e.g. P3.3) –INTO/P3.2 SV00870
Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 DMA TRANSFER Direct Memory Address(DMA) allows an efficient transfer of a block transfer(bulk and interrupt), the buffer needs to be completely filled of data between the host and the local shared memory. Using a up by the DMA write operation before the data is sent to the host. controller. data transfer between the pdiusbd12 main The only exception is at the end of DMA transfer when the reception oint(endpoint 2)and the local shared memory can happen of EOT N will stop DMA write operation and the buffer content will autonomously without local CPU intervention. be sent to the host on the next iN token Preceding any DMA transfer, the local CPU receives from the host For isochronous transfer the local cpu and dma controller has to the necessary setup information and programs the DMA controller guarantee that they are able to sink or source the maximum packet accordingly. Typically, the DMA controller is setup for demand size in one USB frame(1 ms) transfer mode and the byte count register and the address counter are programmed with the right values. In this mode, transfers occur The assertion of DMACK N will automatically selects the main only when the PDIUSBD12 requests them and terminated when the endpoint(endpoint 2) regardless of the current selected endpoint byte count register reaches zero. After the DMA controller has been The DMA operation of the PDIUSBD12 can be interleaved with programmed, the dMa enable bit of the PDIUSBD12 is set by the normal l/o access to other endpoints local cpu to initiate the transfer DMA operation can be terminated by resetting the DMA enable The PDIUSBD12 can be programmed for single cycle DMA or burst register bit or the assertion of EOT N together with DMACK N and mode DMA In single cycle DMA, the DMREQ is deactivated for either rd n or Wr n every single acknowledgement by the DMACK_N before be for PDIUSBD12 supports DMA transfer in a single address mode and it can also work in dual address mode of the dma controller. In the the number of bursts programmed in the device before retuming single address mode, DMA transfer is done via the DREQ, inactive. This process continues until the PDIUSBD12 receives a DMACK N, EOT N. WR N and Rd N control lines. In the dual DMA termination notice through EOT N. This will generate an interrupt to notify the local CPU that DMA operation is completed. address mode, DMREQ, DMACK N and EoT N are Not usec instead CS_N, WR N and RD_N control signals are used. The vO For DMA read operation, the dMREQ will only be activated mode Transfer Protocol of pdiusbd 12 needs to be followed the whenever the buffer is full signifying that the host has successfully source of the DMAC is accessed during the read cycle, and the transferred a packet to the PDIUSBD12. With the double buffering destination accessed during the write cycle. Transfer needs to be scheme, the host can start filling up the second buffer while the first done in two separate bus cycles, storing the data temporarly in the buffer is being read out. This parallel processing increases effective DMAC oughput. For the case when the host does not fill up the buffer ompletely (less than 64 bytes or 128 bytes for single direction ISo ENDPOINT DESCRIPTION configuration), the DMREQ will be deactivated at the last byte of the The PDIUSBD12 endpoints are generic enough to be used by buffer regardless of the current DMA burst count. It will be asserted various device classes ranging from Imaging, Printer, Mass Storage again on the next packet with a refreshed DMA burst count. and Communication device classes. The PDIUSBD12 endpoints can Similarly, for DMA write operation, the DMRI be configured for 4 modes depending on the"Set Mode" command whenever the buffer is not full. when the but The 4 modes are: packet is sent over to the host on the next IN Mode 0(Non-ISO Mode): no Isochronous transfer be reactivated if the transfer was successful. also the double Mode 1(ISO-OUT Mode ): Isochronous output only buffering scheme here will improve throughput For non-isochronous Mode 2(ISo-IN Mode): Isochronous input only tra Mode 3(So-IO Mode) sychronous input and ou
Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 5 DMA TRANSFER Direct Memory Address (DMA) allows an efficient transfer of a block of data between the host and the local shared memory. Using a DMA controller, data transfer between the PDIUSBD12 main endpoint (endpoint 2) and the local shared memory can happen autonomously without local CPU intervention. Preceding any DMA transfer, the local CPU receives from the host the necessary setup information and programs the DMA controller accordingly. Typically, the DMA controller is setup for demand transfer mode and the byte count register and the address counter are programmed with the right values. In this mode, transfers occur only when the PDIUSBD12 requests them and terminated when the byte count register reaches zero. After the DMA controller has been programmed, the DMA enable bit of the PDIUSBD12 is set by the local CPU to initiate the transfer. The PDIUSBD12 can be programmed for single cycle DMA or burst mode DMA. In single cycle DMA, the DMREQ is deactivated for every single acknowledgement by the DMACK_N before being asserted again. In burst mode DMA, the DMREQ is held active for the number of bursts programmed in the device before returning inactive. This process continues until the PDIUSBD12 receives a DMA termination notice through EOT_N. This will generate an interrupt to notify the local CPU that DMA operation is completed. For DMA read operation, the DMREQ will only be activated whenever the buffer is full signifying that the host has successfully transferred a packet to the PDIUSBD12. With the double buffering scheme, the host can start filling up the second buffer while the first buffer is being read out. This parallel processing increases effective throughput. For the case when the host does not fill up the buffer completely (less than 64 bytes or 128 bytes for single direction ISO configuration), the DMREQ will be deactivated at the last byte of the buffer regardless of the current DMA burst count. It will be asserted again on the next packet with a refreshed DMA burst count. Similarly, for DMA write operation, the DMREQ remains active whenever the buffer is not full. When the buffer is filled up, the packet is sent over to the host on the next IN token and DMREQ will be reactivated if the transfer was successful. Also, the double buffering scheme here will improve throughput. For non-isochronous transfer (bulk and interrupt), the buffer needs to be completely filled up by the DMA write operation before the data is sent to the host. The only exception is at the end of DMA transfer when the reception of EOT_N will stop DMA write operation and the buffer content will be sent to the host on the next IN token. For isochronous transfer, the local CPU and DMA controller has to guarantee that they are able to sink or source the maximum packet size in one USB frame (1 ms). The assertion of DMACK_N will automatically selects the main endpoint (endpoint 2) regardless of the current selected endpoint. The DMA operation of the PDIUSBD12 can be interleaved with normal I/O access to other endpoints. DMA operation can be terminated by resetting the DMA enable register bit or the assertion of EOT_N together with DMACK_N and either RD_N or WR_N. PDIUSBD12 supports DMA transfer in a single address mode and it can also work in dual address mode of the DMA controller. In the single address mode, DMA transfer is done via the DREQ, DMACK_N, EOT_N, WR_N and RD_N control lines. In the dual address mode, DMREQ, DMACK_N and EOT_N are NOT used, instead CS_N, WR_N and RD_N control signals are used. The I/O mode Transfer Protocol of PDIUSBD12 needs to be followed. The source of the DMAC is accessed during the read cycle, and the destination accessed during the write cycle. Transfer needs to be done in two separate bus cycles, storing the data temporarily in the DMAC. ENDPOINT DESCRIPTION The PDIUSBD12 endpoints are generic enough to be used by various device classes ranging from Imaging, Printer, Mass Storage and Communication device classes. The PDIUSBD12 endpoints can be configured for 4 modes depending on the “Set Mode” command. The 4 modes are: Mode 0 (Non-ISO Mode): no Isochronous transfer Mode 1 (ISO-OUT Mode): Isochronous output only transfer Mode 2 (ISO-IN Mode): Isochronous input only transfer Mode 3 (ISO-IO Mode): Isochronous input and output transfer