Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 MODE O(NON-ISO MODE ENDPOINT ENDPOINT DIRECTION MAX PACKET SIZE NUMBER TRANSFER TYPE ENDPOINT TYPE Default Generic Out Generic 1 Generic Out OUT MODE 1(ISO-OUT MODE) ENDPOINT ENDPOINT TRANSFER TYPE ENDPOINT TYPE DIRECTION MAX PACKET SIZE NUMBER INDEX (BYTES) Control out OUT 0 Control Generic Out Generic OUT Generic In Generic Isochronous OUT MODE 2(ISO-IN MODE) ENDPOINT ENDPOINT TRANSFER TYPE ENDPOINT TYPE DIRECTION MAX PACKET SIZE (BYTES) 0 Control out OUT Control in Default Generic Out Gene OUT 16 1 Generic Isochronous 1284 MODE 3(ISo-IO MODE ENDPOINT ENDPOINT MAX PACKET SIZE NUMBER INDEX TRANSFER TYPE ENDPOINT TYPE DIRECTION YYTES Control Out OUT ontrol in Default 012345 Generic Out OUT 1 Generic Generic In sychronous out OUT 6 Isochronous In 1. Generic endpoint can be used either as Bulk or Interrupt endpoint 2. The main endpoint (endpoint number 2) is double-buffered to ease synchronization with the real time applications and to increase 3. DMA access is for the main endpoint (endpoint number 2)only. 4. Denotes double buffering The size shown is for a single buffer. MAIN ENDPOINT The main endpoint (endpoint number 2) is special in a few ways. It is the primary endpoint for sinking or sourcing relatively large data. As such, it implements a host of features to ease the task of transferring large data: 1. Double buffering. This allows parallel operation between USB access and local CPU access thus increasing throughput Buffer switching is handled au cally. This results in transparent buffer operatio ports for DMA (Direct Memory Access)operation. This can be interleaved with normal l/O operation to other endpoints 3. Automatic pointer handling during DMA operation. No local CPU intervention is necessary when 'crossing the buffer boundary. 4. Configurable for either isochronous transfer or non-isochronous(bulk and interrupt) transfer
Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 6 MODE 0 (NON-ISO MODE): ENDPOINT NUMBER ENDPOINT INDEX TRANSFER TYPE ENDPOINT TYPE DIRECTION MAX. PACKET SIZE (BYTES) 0 0 Control Out Default OUT 16 0 1 Control In Default IN 16 1 2 Generic Out Generic OUT 16 1 3 Generic In Generic IN 16 2 4 Generic Out Generic OUT 644 2 5 Generic In Generic IN 644 MODE 1 (ISO-OUT MODE): ENDPOINT NUMBER ENDPOINT INDEX TRANSFER TYPE ENDPOINT TYPE DIRECTION MAX. PACKET SIZE (BYTES) 0 0 Control Out Default OUT 16 0 1 Control In Default IN 16 1 2 Generic Out Generic OUT 16 1 3 Generic In Generic IN 16 2 4 Isochronous Out Isochronous OUT 1284 MODE 2 (ISO-IN MODE): ENDPOINT NUMBER ENDPOINT INDEX TRANSFER TYPE ENDPOINT TYPE DIRECTION MAX. PACKET SIZE (BYTES) 0 0 Control Out Default OUT 16 0 1 Control In Default IN 16 1 2 Generic Out Generic OUT 16 1 3 Generic In Generic IN 16 2 5 Isochronous In Isochronous IN 1284 MODE 3 (ISO-IO MODE): ENDPOINT NUMBER ENDPOINT INDEX TRANSFER TYPE ENDPOINT TYPE DIRECTION MAX. PACKET SIZE (BYTES) 0 0 Control Out Default OUT 16 0 1 Control In Default IN 16 1 2 Generic Out Generic OUT 16 1 3 Generic In Generic IN 16 2 4 Isochronous Out Isochronous OUT 644 2 5 Isochronous In Isochronous IN 644 NOTES: 1. Generic endpoint can be used either as Bulk or Interrupt endpoint 2. The main endpoint (endpoint number 2) is double-buffered to ease synchronization with the real time applications and to increase throughput. 3. DMA access is for the main endpoint (endpoint number 2) only. 4. Denotes double buffering. The size shown is for a single buffer. MAIN ENDPOINT The main endpoint (endpoint number 2) is special in a few ways. It is the primary endpoint for sinking or sourcing relatively large data. As such, it implements a host of features to ease the task of transferring large data: 1. Double buffering. This allows parallel operation between USB access and local CPU access thus increasing throughput. Buffer switching is handled automatically. This results in transparent buffer operation. 2. Supports for DMA (Direct Memory Access) operation. This can be interleaved with normal I/O operation to other endpoints. 3. Automatic pointer handling during DMA operation. No local CPU intervention is necessary when ‘crossing’ the buffer boundary. 4. Configurable for either isochronous transfer or non-isochronous (bulk and interrupt) transfer
Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 PINNING Pin configuration DATA0>山 园vou3 ATA<3>4 DATA<4> 6 23 XTAL1 DATA7>回 回 RESET N ALE 10 19 EOT_N DMACK N SUSPEND12 17 DMREQ 16 WR_N INT_N 14 图RDN Pin Description N SYMBOL TYPE DESCRIPTION PINSYMBOLTYPE DESCRIPTION 1 DATA <0> 102 Bit0 of bi-directional data 15 RD_N Read Strobe(Active Low). Slew-rate controlled 16 WR N I Write Strobe(Active Low). DATA <1> 102 Bit 1 of bi-directional data. 3|DATA<2>102 2 of bi-directional data 18DMACK_N IDMA Acknowledge(Active Low). Slew-rate controlled End of DMA Transfer(Active Low) 4DATA <3>102 Bit 3 of bi-directional data. Double up as vbus sensing. EOTN Slew-rate controlled 19 EOT_N I is only valid when asserted together vith dMAcK N and either RD n or 6DATA <4> 102Bit 4 of bi-directional data. 20 RESET N Slew-rate controlled Built-in Power-On-Reset circuit 7DATA <5>102 Bit 5 of bi-directional data. present on chip, so pin can be tied HIGH to Vo 8 DATA <6> 102 Bit 6 of bi-directional data. 21[cL OD8GoodLink LED indicator(Active Low) Slew-rate controlled CRystal Connection 1(6 MHz) 9 DATA <7> 102 Bit 7 of bi-directional data 23XTAL2 o Crystal Connection 2(6 MHz). If Slew-rate controlled extenal clock signal Address Latch Enable The falling dge is used to close the latch of the XTAi, Is connected to XTAL1, ther 10ALE 24v Voltage supply(4.0-5.5v). address/ data bus. Permanently tied low for separate address/ data bus 3 perate the Ic at3su甲py Chip Select(Active Low) A USB D-data line 12 SUSPEND 1, OD4 Device is in Suspend state. 26 AUSB D+ data line 27V 3CLKOUT 02 Programmable Output Clock P3.3V regulated output To opera (slew-rate controlled) the IC at 3. 3v, supply a 3. 3V to both Vcc and VouT33 pins 14 INT_N OD4 Interrupt(Active Low). NOT struction: A0=0 selects the data 28A0 phase. This bit is a don't care in a OD4 Output Open Drain with 4 mA drive OD8 Output Open Drain with 8 mA drive configuration and should be tied high 102 Input and Output with 2 mA drive Output with 4mA drive
Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 7 PINNING Pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 17 18 19 20 21 22 23 24 25 26 27 DATA<0> 28 DATA<1> DATA<2> DATA<3> GND DATA<4> DATA<5> DATA<6> DATA<7> ALE CS_N A0 VOUT3.3 D+ D– VDD XTAL2 XTAL1 RESET_N GL_N EOT_N DMACK_N SUSPEND DMREQ CLKOUT 13 16 WR_N INT_N 14 15 RD_N SV01019 Pin Description PIN SYMBOL TYPE DESCRIPTION 1 DATA <0> IO2 Bit 0 of bi-directional data. Slew-rate controlled. 2 DATA <1> IO2 Bit 1 of bi-directional data. Slew-rate controlled. 3 DATA <2> IO2 Bit 2 of bi-directional data. Slew-rate controlled. 4 DATA <3> IO2 Bit 3 of bi-directional data. Slew-rate controlled. 5 GND P Ground. 6 DATA <4> IO2 Bit 4 of bi-directional data. Slew-rate controlled. 7 DATA <5> IO2 Bit 5 of bi-directional data. Slew-rate controlled. 8 DATA <6> IO2 Bit 6 of bi-directional data. Slew-rate controlled. 9 DATA <7> IO2 Bit 7 of bi-directional data. Slew-rate controlled. 10 ALE I Address Latch Enable. The falling edge is used to close the latch of the address information in a multiplexed address/ data bus. Permanently tied low for separate address/ data bus configuration. 11 CS_N I Chip Select (Active Low). 12 SUSPEND I,OD4 Device is in Suspend state. 13 CLKOUT O2 Programmable Output Clock (slew-rate controlled). 14 INT_N OD4 Interrupt (Active Low). NOTE: 1. O2 : Output with 2 mA drive OD4 : Output Open Drain with 4 mA drive OD8 : Output Open Drain with 8 mA drive IO2 : Input and Output with 2 mA drive O4 : Output with 4mA drive PIN SYMBOL TYPE DESCRIPTION 15 RD_N I Read Strobe (Active Low). 16 WR_N I Write Strobe (Active Low). 17 DMREQ O4 DMA Request. 18 DMACK_N I DMA Acknowledge (Active Low). 19 EOT_N I End of DMA Transfer (Active Low). Double up as Vbus sensing. EOT_N is only valid when asserted together with DMACK_N and either RD_N or WR_N. 20 RESET_N I Reset (Active Low and asynchronous). Built-in Power-On-Reset circuit present on chip, so pin can be tied HIGH to VCC. 21 GL_N OD8 GoodLink LED indicator (Active Low) 22 XTAL1 I Crystal Connection 1 (6 MHz) 23 XTAL2 O Crystal Connection 2 (6 MHz). If external clock signal, instead of crystal, is connected to XTAL1, then XTAL2 should be floated. 24 VCC P Voltage supply (4.0 – 5.5V). To operate the IC at 3.3V, supply 3.3V to both VCC and VOUT3.3 pins. 25 D– A USB D– data line 26 D+ A USB D+ data line 27 VOUT3.3 P 3.3V regulated output. To operate the IC at 3.3V, supply a 3.3V to both VCC and VOUT3.3 pins 28 A0 I Address bit. A0=1 selects command instruction; A0=0 selects the data phase. This bit is a don’t care in a multiplexed address and data bus configuration and should be tied high
Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 COMMAND SUMMARY COMMANDNAME RECIPIENT DATA PHASE Initialization Commands Set Address/Enable Device Write 1 byte Set Endpoint Enable Device Write 1 byte Set DMA FBh Write/Read 1 byte Data Flow Commands Select Endpoint Control out Read 1 byte(optional) Control IN 01h Read 1 byte(optional) Endpoint 1 OUT Read 1 byte(optional) Endpoint 1 IN Read 1 byte(optional Endpoint 2 OUT Read 1 byte(optional) Endpoint 2 IN 05h Read 1 byte(optional) Transaction Status Control oUt Read 1 byte Endpoint 1 OUT 42h Endpoint 1 IN Read 1 byte ndpoint 2 OU Read1byte Read 1 byte ead Buffer Selected Endpoint FO Write Buffer Selected Endpoint F tes Set Endpoint Status Control oUT Write 1 byte Control IN 41h Write 1 byte Endpoint 1 OUT 42h Write 1 byte Write 1 byte dpoint 2 OUT 44h Write 1 byte Endpoint 2 IN 45h Write 1 byte Acknowledge Setup Selected Endpoint Validate Buffer Selected Endpoint FAh General Commands Send resum F6h Read Current Frame Number Read 1 or 2 byte
Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 8 COMMAND SUMMARY COMMAND NAME RECIPIENT CODING DATA PHASE Initialization Commands Set Address/Enable Device D0h Write 1 byte Set Endpoint Enable Device D8h Write 1 byte Set Mode Device F3h Write 2 bytes Set DMA Device FBh Write/Read 1 byte Data Flow Commands Read Interrupt Register Device F4h Read 2 bytes Select Endpoint Control OUT 00h Read 1 byte (optional) Control IN 01h Read 1 byte (optional) Endpoint 1 OUT 02h Read 1 byte (optional) Endpoint 1 IN 03h Read 1 byte (optional) Endpoint 2 OUT 04h Read 1 byte (optional) Endpoint 2 IN 05h Read 1 byte (optional) Read Last Transaction Status Control OUT 40h Read 1 byte Control IN 41h Read 1 byte Endpoint 1 OUT 42h Read 1 byte Endpoint 1 IN 43h Read 1 byte Endpoint 2 OUT 44h Read 1 byte Endpoint 2 IN 45h Read 1 byte Read Buffer Selected Endpoint F0h Read n bytes Write Buffer Selected Endpoint F0h Write n bytes Set Endpoint Status Control OUT 40h Write 1 byte Control IN 41h Write 1 byte Endpoint 1 OUT 42h Write 1 byte Endpoint 1 IN 43h Write 1 byte Endpoint 2 OUT 44h Write 1 byte Endpoint 2 IN 45h Write 1 byte Acknowledge Setup Selected Endpoint F1h None Clear Buffer Selected Endpoint F2h None Validate Buffer Selected Endpoint FAh None General Commands Send Resume F6h None Read Current Frame Number F5h Read 1 or 2 bytes