G PHILIPS Philips semiconductors Interconnectivity 23 September 1998 Firmware Programming Guide for PDIUSBD12 Version 1.0 Philips Semiconductors- Asia Product Innovation Centre Visithttp:/www.flexiusb.com
Philips Semiconductors Interconnectivity _______________________________________________________________________________________________ Philips Semiconductors - Asia Product Innovation Centre Visit http://www.flexiusb.com 23 September 1998 Firmware Programming Guide for PDIUSBD12 Version 1.0
Interconnectivity Page 2 of 22 Firmware Programming guide for PDIUSBD12 This is a legal agreement between you(either an individual or an entity and Philips Semiconductors. By accepting this product, you indicate your agreement to the disclaimer specified as follows DISCLAIMER PRODUCT IS DEEMED ACCEPTED BY RECIPIENT. THE PRODUCT IS PROVIDED "AS IS WITHOUT WARRANTY OF ANY KIND. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW. PHILIPS SEMICONDUCTORS FURTHER DISCLAIMS ALL WARRANTIES. INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANT ABILITY. FITNESS FOR A PARTICULAR PURPOSE. AND NONINFRINGEMENT. THE ENTIRE RISK ARISING OUT OF THE USE OR PERFORMANCE OF THE PRODUCT AND DOCUMENTATION REMAINS WITH THE RECIPIENT TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW IN NO EVENT SHALL PHILIPS SEMICONDUCTORS OR ITS SUPPLIERS BE LIABLE FOR ANY CONSEQUENTIAL, INCIDENTAL, DIRECT, INDIRECT. SPECIAL. PUNITIVE. OR OTHER DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS. BUSINESS INTERRUPTION. LOSS OF BUSINESS INFORMATION. OR OTHER PECUNIARY LOSS) ARISING OUT OF THIS AGREEMENT OR THE USE OF OR INABILITY TO USE THE PRODUCT. EVEN IF PHILIPS SEMICONDUCTORS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Philips Semiconductors-Asia Product Innovation Centre
Interconnectivity Page 2 of 22 Firmware Programming Guide for PDIUSBD12 _______________________________________________________________________________________________ Philips Semiconductors - Asia Product Innovation Centre Visit http://www.flexiusb.com This is a legal agreement between you (either an individual or an entity) and Philips Semiconductors. By accepting this product, you indicate your agreement to the disclaimer specified as follows: DISCLAIMER PRODUCT IS DEEMED ACCEPTED BY RECIPIENT. THE PRODUCT IS PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, PHILIPS SEMICONDUCTORS FURTHER DISCLAIMS ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANT ABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. THE ENTIRE RISK ARISING OUT OF THE USE OR PERFORMANCE OF THE PRODUCT AND DOCUMENTATION REMAINS WITH THE RECIPIENT. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL PHILIPS SEMICONDUCTORS OR ITS SUPPLIERS BE LIABLE FOR ANY CONSEQUENTIAL, INCIDENTAL, DIRECT, INDIRECT, SPECIAL, PUNITIVE, OR OTHER DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OUT OF THIS AGREEMENT OR THE USE OF OR INABILITY TO USE THE PRODUCT, EVEN IF PHILIPS SEMICONDUCTORS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
Interconnectivity Page 3 of 22 Firmware Programming guide for PDIUSBD12 Table of contents 1 INTRODUCTION 2 ARCHITECTURE 2. 1 FIRMWARE STRUCTURE 1. Hardware Abstraction Layer- EPPHAL C 2.1.2 PDIUSBD/2 Command Interface-DI2CIC 2.1.3 Interrupt Service Routine-ISRC 2.1.4 Main Loop- MAINLOOP C 455555666 2.1.5 Protocol Laver-CHAP 9.C. PROTODMA C. 2.2 PORTING THE FIRMWARE TO OTHER CPU PLATFORM 2.3 USING THE FIRMWARE IN POLLING MODE 3 HARDWARE ABSTRACTION LAYER 4 PDIUSBD12 COMMAND INTERFACE 5 INTERRUPT SERVICE ROUTINE 667789 5.1 BUS RESET AND SUSPEND CHANGE 5.2 CONTROL ENDPOINT HANDLER 5.3 GENERIC ENDPOINT HANDLER 5. 4 MAIN ENDPOINT HANDLER 5.5 EOT HANDLER o3334 6 MAIN LOOP 7 CHAPTER 9 PROTOCOL 7.1 CLEAR FEATURE REQUEST 7.2 GET STATUS REQUEST. 7.3 SET ADDRESS REQUEST 16 4 GET CONFIG REQUEST 7.5 GET DESCRIPTOR REQUEST 7.6 SET CONFIG REQUEST 7.7 GET/SET INTERFACE REQUEST 18 7.8 SET FEATURE REQUEST 8 DMA SUPPORT 8.1 INTRODUCTION TO PROTOCOL BASED DMA OPERATION 8.2 DEVICES DMA STATES 8.3 DMA CONFIGURATION REGISTER 8.4 SETUP DMA REQUEST 8.5 HOST SIDE PROGRAMMING CONSIDERATIONS Philips Semiconductors- Asia Product Innovation Centre
Interconnectivity Page 3 of 22 Firmware Programming Guide for PDIUSBD12 _______________________________________________________________________________________________ Philips Semiconductors - Asia Product Innovation Centre Visit http://www.flexiusb.com Table of Contents 1 INTRODUCTION........................................................................................................................................... 4 2 ARCHITECTURE.......................................................................................................................................... 5 2.1 FIRMWARE STRUCTURE ............................................................................................................................... 5 2.1.1 Hardware Abstraction Layer - EPPHAL.C ........................................................................................... 5 2.1.2 PDIUSBD12 Command Interface - D12CI.C........................................................................................ 5 2.1.3 Interrupt Service Routine - ISR.C ......................................................................................................... 5 2.1.4 Main Loop - MAINLOOP.C ................................................................................................................. 6 2.1.5 Protocol Layer - CHAP_9.C, PROTODMA.C....................................................................................... 6 2.2 PORTING THE FIRMWARE TO OTHER CPU PLATFORM ................................................................................... 6 2.3 USING THE FIRMWARE IN POLLING MODE .................................................................................................... 6 3 HARDWARE ABSTRACTION LAYER ....................................................................................................... 7 4 PDIUSBD12 COMMAND INTERFACE........................................................................................................ 7 5 INTERRUPT SERVICE ROUTINE .............................................................................................................. 8 5.1 BUS RESET AND SUSPEND CHANGE.............................................................................................................. 9 5.2 CONTROL ENDPOINT HANDLER.................................................................................................................. 10 5.3 GENERIC ENDPOINT HANDLER................................................................................................................... 13 5.4 MAIN ENDPOINT HANDLER........................................................................................................................ 13 5.5 EOT HANDLER ......................................................................................................................................... 13 6 MAIN LOOP................................................................................................................................................. 14 7 CHAPTER 9 PROTOCOL........................................................................................................................... 15 7.1 CLEAR FEATURE REQUEST ........................................................................................................................ 15 7.2 GET STATUS REQUEST............................................................................................................................... 16 7.3 SET ADDRESS REQUEST............................................................................................................................. 16 7.4 GET CONFIG REQUEST............................................................................................................................... 17 7.5 GET DESCRIPTOR REQUEST ....................................................................................................................... 17 7.6 SET CONFIG REQUEST ............................................................................................................................... 18 7.7 GET/SET INTERFACE REQUEST................................................................................................................... 18 7.8 SET FEATURE REQUEST ............................................................................................................................. 19 8 DMA SUPPORT............................................................................................................................................ 20 8.1 INTRODUCTION TO PROTOCOL BASED DMA OPERATION ............................................................................ 20 8.2 DEVICE'S DMA STATES............................................................................................................................. 20 8.3 DMA CONFIGURATION REGISTER.............................................................................................................. 21 8.4 SETUP DMA REQUEST .............................................................................................................................. 21 8.5 HOST SIDE PROGRAMMING CONSIDERATIONS............................................................................................. 22
Interconnectivity Page 4 of 22 Firmware Programming guide for PDIUSBD12 1 Introduction PDIUSBD12 is a high-speed USB interface device with parallel bus and local DMA transfer capability. The objective of the recommended firmware design is to enable PDIUSBD 12 to achieve the fastest transfer rate over USB Peripheral devices such as the printer, scanner, external mass storage, and digital camera can use PDIUSBD12 in transferring data over USB. The CPUs in these devices are very busy in handling many tasks like device control and data and image processing. The firmware of PDIUSBD 12 is designed to be fully interrupt-driven While CPU is doing its foreground task, the USB transfer is being handled in the background. This assures best transfer rate and better software structure and also simplifies programming and debugging The data exchange between the background ISR (Interrupt Service Routine) and the foreground Main Loop is achieved by event flags and data buffers. For example, the PDIUSBD12 Main bulk out endpoint can use a circular data buffer. When PDIUSBD12 receives a data packet from USB, an interrupt request is generated to the CPU and the CPU will service ISR immediately. Inside the ISR, the firmware moves the data packet to the ircular buffer from pdiusbd12 's internal buffer and then clears the pdiusbd i2's internal buffer to enable PDIUSBD12 to receive new packet. The CPU can continue its current foreground task until completion, e.g printing current page. Then it returns to the main loop, checks the circular buffers for new data, and starts another foreground task RXRP, Read Pointer maintained by main loop Main loop in foreground ISR in background Circular data buffer RXWP, Write Pointer maintained by ISr With this structure, the Main Loop does not care whether the data source is from USB, serial port, or parallel port. The Main Loop only checks the circular buffer for new data to be processed. This concept is very important. Thus, the Main Loop program can target on data processing and the ISr can do the job of data transfer at the fastest speed possible Similarly, the control endpoint uses the same concept in data packet handling. The ISR receives and stores control transfers in data buffers and sets the corresponding flag registers. The main loop will dispatch the request to protocol handling routines. Since all the standard device, class, and vendor requests are processed in protocol handling routines, ISR can maintain its efficiency. Also, when new request is added, only modification at the protocol level is needed llips Semiconductors-Asia Product Innovation Centre Visithttp://www.fler
Interconnectivity Page 4 of 22 Firmware Programming Guide for PDIUSBD12 Philips Semiconductors - Asia Product Innovation Centre Visit http://www.flexiusb.com 1. Introduction PDIUSBD12 is a high-speed USB interface device with parallel bus and local DMA transfer capability. The objective of the recommended firmware design is to enable PDIUSBD12 to achieve the fastest transfer rate over USB. Peripheral devices such as the printer, scanner, external mass storage, and digital camera can use PDIUSBD12 in transferring data over USB. The CPUs in these devices are very busy in handling many tasks like device control and data and image processing. The firmware of PDIUSBD12 is designed to be fully interrupt-driven. While CPU is doing its foreground task, the USB transfer is being handled in the background. This assures best transfer rate and better software structure and also simplifies programming and debugging. The data exchange between the background ISR (Interrupt Service Routine) and the foreground Main Loop is achieved by event flags and data buffers. For example, the PDIUSBD12 Main bulk out endpoint can use a circular data buffer. When PDIUSBD12 receives a data packet from USB, an interrupt request is generated to the CPU and the CPU will service ISR immediately. Inside the ISR, the firmware moves the data packet to the circular buffer from PDIUSBD12's internal buffer and then clears the PDIUSBD12's internal buffer to enable PDIUSBD12 to receive new packet. The CPU can continue its current foreground task until completion, e.g. printing current page. Then it returns to the main loop, checks the circular buffers for new data, and starts another foreground task. With this structure, the Main Loop does not care whether the data source is from USB, serial port, or parallel port. The Main Loop only checks the circular buffer for new data to be processed. This concept is very important. Thus, the Main Loop program can target on data processing and the ISR can do the job of data transfer at the fastest speed possible. Similarly, the control endpoint uses the same concept in data packet handling. The ISR receives and stores control transfers in data buffers and sets the corresponding flag registers. The main loop will dispatch the request to protocol handling routines. Since all the standard device, class, and vendor requests are processed in protocol handling routines, ISR can maintain its efficiency. Also, when new request is added, only modification at the protocol level is needed. ISR in background Main loop in foreground RXWP, Write Pointer maintained by ISR RXRP, Read Pointer maintained by main loop Circular data buffer
Interconnectivity Page 5 of 22 Firmware Programming guide for PDIUSBD12 2. Architecture 2.1 Firmware Structure The firmware for the evaluation board consists of 6 building blocks. They are as folle ED. Process USB Bus Event. etc. MAINLOOP. C ndard Request Vendor request PROTODMA.C Interrupt Service Routine ISR. C Hardware Abstraction Layer EPPHAL C 2.1.1 Hardware Abstraction Layer -EPPHALC This is the lowest layer code in the firmware, which performs hardware dependent I/O access to PDIUSBD12 as well as Evaluation Board hardware. When porting the firmware to other CPU platforms, this part of code al ways needs modifications or additions 2.1.2 PDIUSBD12 Command Interface-D12CL C To further simplify programming with PDIUSBD 12, the firmware defines a set of command interfaces, which encapsulate all the functions used to access PDIUSBD12 2.1.3 Interrupt service Routine-ISR C This part of the code handles interrupt generated by PDIUSBD12. It retrieves data from PDIUSBD12's internal FIFO to CPU memory, and set up proper event flags to inform Main Loop program for processing llips Semiconductors-Asia Product Innovation Centre Visithttp://www.flexi
Interconnectivity Page 5 of 22 Firmware Programming Guide for PDIUSBD12 Philips Semiconductors - Asia Product Innovation Centre Visit http://www.flexiusb.com 2. Architecture 2.1 Firmware Structure The firmware for the evaluation board consists of 6 building blocks. They are as follows: 2.1.1 Hardware Abstraction Layer - EPPHAL.C This is the lowest layer code in the firmware, which performs hardware dependent I/O access to PDIUSBD12, as well as Evaluation Board hardware. When porting the firmware to other CPU platforms, this part of code always needs modifications or additions. 2.1.2 PDIUSBD12 Command Interface - D12CI.C To further simplify programming with PDIUSBD12, the firmware defines a set of command interfaces, which encapsulate all the functions used to access PDIUSBD12. 2.1.3 Interrupt Service Routine - ISR.C This part of the code handles interrupt generated by PDIUSBD12. It retrieves data from PDIUSBD12's internal FIFO to CPU memory, and set up proper event flags to inform Main Loop program for processing. Hardware Abstraction Layer EPPHAL.C PDIUSBD12 Command Interface D12CI.C Main Loop: Dispatch USB Request, Read Test Keys, Control LED, Process USB Bus Event, etc. MAINLOOP.C Interrupt Service Routine ISR.C Standard Request CHAP_9.C Vendor Request PROTODMA.C