MiPS R3000 Instruction set Architecture (Summary) Registers 指令类型 Load/store R0-R31 Computational Jump and branch Floating Point 》 coprocessor PC Memory Management HI Special LO 3种指令格式:a32 bits wide R型 OP rs sa funct 型oPr rS t immediate J型 OP jump target 1/30/2021
1/30/2021 中国科学技术大学 25 • 指令类型 – Load/Store – Computational – Jump and Branch – Floating Point » coprocessor – Memory Management – Special R0 - R31 PC HI LO OP OP OP rs rt rd sa funct rs rt immediate jump target 3 种指令格式: all 32 bits wide Registers MIPS R3000 Instruction Set Architecture (Summary) J 型 I 型 R型
Logic Designer's view 计算机组成与实现 ISA Level FUs interconnect 计算机组成( Computer Organization or Microarchitecture):lsA的逻辑实现 物理机器级中的数据流和控制流的组成以及逻辑设计等 计算机实现( Computer Implementation):计算机组成 的物理实现 cPU, MEMORY等的物理结构,器件的集成度、速度,模块、插件、 底板的划分与连接、信号传输、电源、冷却及整机装配技术等 例如 确定指令系统中是否有乘法指令( Architecture) 确定用加法器实现乘法还是用专门的乘法实现( Organization) 器件的选定及所用的微组装技术( Implementation) 1/30/2021 中国科学技术大学
1/30/2021 中国科学技术大学 26 Logic Designer's View ISA Level FUs & Interconnect • 计算机组成（Computer Organization or Microarchitecture): ISA的逻辑实现 – 物理机器级中的数据流和控制流的组成以及逻辑设计等 • 计算机实现（Computer Implementation):计算机组成 的物理实现 – CPU ，MEMORY等的物理结构，器件的集成度、速度，模块、插件、 底板的划分与连接、信号传输、电源、冷却及整机装配技术等 • 例如 – 确定指令系统中是否有乘法指令(Architecture) – 确定用加法器实现乘法 还是用专门的乘法实现（Organization) – 器件的选定及所用的微组装技术（Implementation) 计算机组成与实现
Example Organization TI Super SPaRctm TMs390Z50 in Sun SPARCstation20 MBUs Module SuperSPARC ■■■■ ■■□■■■■ Floating-point Unit □■■■■■■□ DRAM Integer Unit MBuS Controller Inst Ref Data L64852 MBus control CacheMMU M-S Adapter Cache STDIO SBus serial Store SCSI d SBUs mouse Buffer DMA Ethernet audio RTC Bus Interface SBus Boot PROM Cards Flo 1/30/2021 中国科学技术 27
1/30/2021 中国科学技术大学 27 Example Organization • TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20 Boot PROM Floating-point Unit Integer Unit Inst Cache Ref MMU Data Cache Store Buffer Bus Interface SuperSPARC L2 $ CC MBus Module MBus L64852 MBus control M-S Adapter SBus DRAM Controller SBus DMA SCSI Ethernet STDIO serial kbd mouse audio RTC Floppy SBus Cards
体系结构vs.微结构 Architecture /Instruction Set Architecture(ISA) Class of IsA: register-memory or register-register architectures Programmer visible state(Register and Memory Addressing Modes: how memory addresses are computed Data types and sizes for integer and floating-point operands Instructions, encoding, and operation Exception and Interrupt semantics Microarchitecture/Organization Tradeoffs on how to implement the Isa for speed, energy, cost Pipeline width and depth, cache size, peak power, bus width execution order, etc 1/30/2021 中国科学技术大学 28
体系结构 vs.微结构 • Architecture / Instruction Set Architecture (ISA) – Class of ISA: register-memory or register-register architectures – Programmer visible state (Register and Memory) – Addressing Modes: how memory addresses are computed – Data types and sizes for integer and floating-point operands – Instructions, encoding, and operation – Exception and Interrupt semantics • Microarchitecture / Organization – Tradeoffs on how to implement the ISA for speed, energy, cost – Pipeline width and depth, cache size, peak power, bus width, execution order, etc 1/30/2021 中国科学技术大学 28
计犷机体系结构中的经典思翘 1. Design for Moores Law 2 Abstraction to Simplify Design 3. Make the common case Fast 4. Dependability via Redundancy 5. Memory Hierarchy 6. Performance via Parallelism/Pipelining/prediction 1/30/2021 中国科学技术大学
计算机体系结构中的经典思想 1. Design for Moore’s Law 2. Abstraction to Simplify Design 3. Make the Common Case Fast 4. Dependability via Redundancy 5. Memory Hierarchy 6. Performance via Parallelism/Pipelining/Prediction 1/30/2021 中国科学技术大学 29