Data Hazards ◼ Instruction having register R as source follows shortly after instruction having register R as destination ◼ Common condition, don’t want to slow down pipeline Control Hazards ◼ Mispredict conditional branch ⚫ Our design predicts all branches as being taken ⚫ Naïve pipeline executes two extra instructions ◼ Getting return address for ret instruction ⚫ PIPE- executes three extra instructions Making Sure It Really Works ◼ What if multiple special cases happen simultaneously?

◼ Goal ◼ Difficulties Creating a Pipelined Y86 Processor ◼ Rearranging SEQ ◼ Inserting pipeline registers ◼ Problems with data and control hazards

复旦大学：《计算机原理 Computer System》课程PPT课件_09、10 Sequential CPU Implementation

复旦大学：《计算机原理 Computer System》课程PPT课件_Processor Architecture

• Struct • Union • Alignment • Pointer – Declaration – referencing, deferencing – memory allocation, memory free • Buffer overflow • Suggested reading • Stack evaluation • Data movement • Set special data • Arithmetic operation • Comparison • Suggested reading

• Data manipulation • Control structure • Suggested reading

• Data movement • Data manipulation • Control structure • Suggested reading

• Compiler drivers • History of the Intel IA-32 architecture • Assembly code and object code • Memory and Registers • Addressing Mode • Data Formats • Suggested reading

• Arithmetic Operations – overflow – Unsigned addition, multiplication – Signed addition, negation, multiplication – Using Shift to perform power-of-2 multiply/divide • Suggested reading

• Encodings – Unsigned and two’s complement • Conversions – Signed vs. unsigned – Long vs. short • Suggested reading