13.1 Introduction 13.2 Parallel Multipliers 13.3 Interleaved Floor-Plan and Bit-Plane-Based Digital Filters 13.4 Bit-Serial Multipliers 13.5 Bit-Serial Filter 13.6 Canonic Signed Digit Arithmetic

11.1 Introduction 11.2.1 Scaling Operation 11.2.2 Round-off Noise 11.3 State Variable Description of Digital Filters 11.4 Scaling and Round-off Noise Computation 11.6 Round-off Noise Computation Using State Variable Description 11.7 Slow-Down, Retiming, and Pipelining

9.1 Introduction 9.2 Parallel FIR filters 9.3 DCT and IDCT

8.1 Introduction 8.2 Cook-Toom algorithm 8.3 Winograd algorithm 8.4 Iterated convolution

10.1 Introduction 10.2 Pipeline interleaving in digital filters 10.3.1 Pipelining for 1st-Order IIR Filters 10.3.2 Look-Ahead Pipelining with Power-of-2 Decomposition 10.3.3 Look-Ahead Pipelining with General Decomposition 10.4 Pipelining in Higher-order IIR Digital Filters 10.5 Parallel Processing in IIR Filters

电子科技大学：《DSP算法实现技术与架构 VLSI Digital Signal Processing Systems Design and Implementation》课程教学资源（课件讲稿）Chapter 07 脉动阵列 Systolic Architecture

电子科技大学：《DSP算法实现技术与架构 VLSI Digital Signal Processing Systems Design and Implementation》课程教学资源（课件讲稿）Chapter 06 折叠 Folding

5.1 Introduction 5.2 Unfolding algorithm 5.3 Properties of unfolding 5.4 Critical path and retiming 5.5 Applications of unfolding

4.1 Introduction 4.2.1 Quantitative description 4.2.2 Properties of retiming 4.3 Solving systems inequalities 4.4 Retiming techniques 4.4.1 Cutset retiming and pipelining 4.4.2 Clock period minimization 4.4.3 register minimization

电子科技大学：《DSP算法实现技术与架构 VLSI Digital Signal Processing Systems Design and Implementation》课程教学资源（课件讲稿）Chapter 03 流水与并行 Pipelining and Parallel Processing