查询MC1496供应商 MG1496,Mc1496B Balanced modulators ON Demodulators These devices were designed for use where the output voltage is a product of an input voltage(signal) and a switching function(carrier) ON Semiconductor Typical applications include suppressed carrier and amplitude modulation, synchronous detection, FM detection, phase detection, http:/lonsemi.com and chopper applications. See On Semiconductor Application Note an531 for additional design information. SOIC-14 D SUFFIX Features CASE 751A Excellent Carrier Suppression -65 dB typ(@0.5 MHz 50 dB typ@ 10 MHz Adjustable Gain and Signal Handling PDIP-14 Balanced Inputs and Outputs P SUFFⅨX High Common Mode Rejection -85 dB Typical CASE 646 e This device contains 8 active transistors Pb-Free Package is Available* PIN CONNECTIONS Signal Input 1 图v Gain Adjust 13N/C 21⑩ ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet DEVICE MARKING INFORMATION See general marking information in the device marking section on page 12 of this data sheet. and soldering details, please download the ON emiconductor Soldering and Mounting Techniques Reference Manual. SOLDERRM/D Publication Order Numb April, 2004--Rev 9 MC1496/D
Semiconductor Components Industries, LLC, 2004 April, 2004 − Rev. 9 1 Publication Order Number: MC1496/D MC1496, MC1496B Balanced Modulators/ Demodulators These devices were designed for use where the output voltage is a product of an input voltage (signal) and a switching function (carrier). Typical applications include suppressed carrier and amplitude modulation, synchronous detection, FM detection, phase detection, and chopper applications. See ON Semiconductor Application Note AN531 for additional design information. Features • Excellent Carrier Suppression −65 dB typ @ 0.5 MHz −50 dB typ @ 10 MHz • Adjustable Gain and Signal Handling • Balanced Inputs and Outputs • High Common Mode Rejection −85 dB Typical • This Device Contains 8 Active Transistors • Pb−Free Package is Available* http://onsemi.com SOIC−14 D SUFFIX CASE 751A 14 1 14 1 PDIP−14 P SUFFIX CASE 646 PIN CONNECTIONS Signal Input 1 2 3 4 5 6 7 10 11 14 13 12 9 N/C Output Bias Signal Input Gain Adjust Gain Adjust 8 Input Carrier VEE N/C Output N/C Carrier Input N/C See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. ORDERING INFORMATION See general marking information in the device marking section on page 12 of this data sheet. DEVICE MARKING INFORMATION *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 查询MC1496供应商
Mc1496,Mc1496B =10kH Ic= 500 kHz, Is= 1.0 kHz Figure 1. Suppressed Carrier Output Figure 2. Suppressed Carrier Spectrum Waveform ls= 1.0 kHz 499 KHz 500 KHz 501 KHZ Figure 3. Amplitude Modulation Figure 4. Amplitude-Modulation Spectrum Output Waveform MAXIMUM RATINGS (TA= 25.C, unless otherwise noted Rating Symbol Unit 6-V8,v10V1,v12-V8,V12-V10,v8-V4.V8-V1,V10-V4,v6-V10.V2-V5,V3-V5) Differential Input Signal v8-V10 +5.0 Vdc 4-V1±5+15Re) Maximum Bias Current l5 Thermal Resistance. Junction-to -Air R 100 Plastic Dual In-Line Package Operating Ambient Temperature Range MC1496 0to+70°c MC1496B -40to+125 Storage Temperature Range sg|-65to+150° Electrostatic Discharge Sensitivity(ESD) man Body Model(HBM) 2000 Machine Model (MM) Maximum ratings are those values beyond which device damage can occur. Maxi values(not nomal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation i not implied damage may occur and reliability may be affected. httpllonsemi.com
MC1496, MC1496B http://onsemi.com 2 IC = 500 kHz, IS = 1.0 kHz IC = 500 kHz IS = 1.0 kHz 60 40 20 0 Log Scale Id 499 kHz 500 kHz 501 kHz IC = 500 kHz IS = 1.0 kHz IC = 500 kHz IS = 1.0 kHz 499 kHz 500 kHz 501 kHz Linear Scale 10 8.0 6.0 4.0 2.0 0 Figure 1. Suppressed Carrier Output Waveform Figure 2. Suppressed Carrier Spectrum Figure 3. Amplitude Modulation Output Waveform Figure 4. Amplitude−Modulation Spectrum MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.) Rating Symbol Value Unit Applied Voltage (V6−V8, V10−V1, V12−V8, V12−V10, V8−V4, V8−V1, V10−V4, V6−V10, V2−V5, V3−V5) V 30 Vdc Differential Input Signal V8 − V10 V4 − V1 +5.0 ±(5+I5Re) Vdc Maximum Bias Current I5 10 mA Thermal Resistance, Junction−to−Air Plastic Dual In−Line Package RJA 100 °C/W Operating Ambient Temperature Range MC1496 MC1496B TA 0 to +70 −40 to +125 °C Storage Temperature Range Tstg −65 to +150 °C Electrostatic Discharge Sensitivity (ESD) Human Body Model (HBM) Machine Model (MM) ESD 2000 400 V Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
Mc1496,Mc1496B ELECTRICAL CHARACTERISTICS (Vcc=12 Vdc, VEE=-80 Vdc, 15=1.0 mAdc, RL=3.9 k@2, R,=1.0 k@, TA=Tlow to Thigh, all input and output characteristics are single-ended, unless otherwise noted )(Note 1) Characteristic Fig.Note Symbol Min Typ MaxUnit Carrier Feedthrough uVms Vc=60 mVrms sine wave and fc=1.0 kHz offset adjusted to zer fc =10 MHz Vc=300 mVpp square wave: offset adjusted to zero fc =1.0 kHz offset not adjusted CS fc 500 kHz, 60 mVrms sine wave 65 fc= 10 MHz, 60 mVm Transadmittance Bandwidth(Magnitude)(Rl= 50 2) Carrier Input Port, Vc=60 mVrms sine wave Signal Input Port, Vs= 300 mVrms sine wave 80 Vcl =0.5 Vdc Signal Gain (Vs= 100 mVrms, f=1.0 kHz; VCl= 0. 5 Vdc) 3 2535 Single-Ended Input Impedance, Signal Port, f= 5.0 MHz Parallel Input Capacitance p Parallel Output Resistance Parallel Output Capacitance 50 Input Bias Current Input Offset Current 0.7 los=11-4;loc=8-110 0770 Average Temperature Coefficient of Input Offset Current ITCliol 2.0 DAC TA=-55cto+125°C) Output Offset Current(16-19) Average Temperature Coefficient of Output Offset Current TclooI (TA=-55Cto+125°C) Common-Mode Input Swing, Signal Port, fs=1.0 kHz Common-Mode Gain, Signal Port, fs =1.0 kHz, Ncl= 0.5 vdc ACM Common-Mode Quiescent Output Voltage(Pin 6 or Pin 9) Differential Output Voltage Swing Capability Power Supply Current 16+112 Icc 14 3050 DC Power Dissipa 1. Tlow =0C for MC1496 Thigh -+125C for MC1496B =+70° for mc1496 40C for MC1496B httpllonsemi.com
MC1496, MC1496B http://onsemi.com 3 ELECTRICAL CHARACTERISTICS (VCC = 12 Vdc, VEE = −8.0 Vdc, I5 = 1.0 mAdc, RL = 3.9 k, Re = 1.0 k, TA = Tlow to Thigh, all input and output characteristics are single−ended, unless otherwise noted.) (Note 1) Characteristic Fig. Note Symbol Min Typ Max Unit Carrier Feedthrough VC = 60 mVrms sine wave and offset adjusted to zero VC = 300 mVpp square wave: offset adjusted to zero offset not adjusted fC = 1.0 kHz fC = 10 MHz fC = 1.0 kHz fC = 1.0 kHz 5 1 VCFT − − − − 40 140 0.04 20 − − 0.4 200 Vrms mVrms Carrier Suppression fS = 10 kHz, 300 mVrms fC = 500 kHz, 60 mVrms sine wave fC = 10 MHz, 60 mVrms sine wave 5 2 VCS 40 − 65 50 − − dB k Transadmittance Bandwidth (Magnitude) (RL = 50 ) Carrier Input Port, VC = 60 mVrms sine wave fS = 1.0 kHz, 300 mVrms sine wave Signal Input Port, VS = 300 mVrms sine wave |VC| = 0.5 Vdc 8 8 BW3dB − − 300 80 − − MHz Signal Gain (VS = 100 mVrms, f = 1.0 kHz; |VC|= 0.5 Vdc) 10 3 AVS 2.5 3.5 − V/V Single−Ended Input Impedance, Signal Port, f = 5.0 MHz Parallel Input Resistance Parallel Input Capacitance 6 − rip cip − − 200 2.0 − − k pF Single−Ended Output Impedance, f = 10 MHz Parallel Output Resistance Parallel Output Capacitance 6 − rop coo − − 40 5.0 − − k pF Input Bias Current 7 − I 12 30 A I bS I1 I4 2 ; IbC I8 I10 2 IbS IbC − − 12 12 30 30 Input Offset Current IioS = I1−I4; IioC = I8−I10 7 − IioS IioC − − 0.7 0.7 7.0 7.0 A Average Temperature Coefficient of Input Offset Current (TA = −55°C to +125°C) 7 − TCIio − 2.0 − nA/°C Output Offset Current (I6−I9) 7 − Ioo − 14 80 A Average Temperature Coefficient of Output Offset Current (TA = −55°C to +125°C) 7 − TCIoo − 90 − nA/°C Common−Mode Input Swing, Signal Port, fS = 1.0 kHz 9 4 CMV − 5.0 − Vpp Common−Mode Gain, Signal Port, fS = 1.0 kHz, |VC|= 0.5 Vdc 9 − ACM − −85 − dB Common−Mode Quiescent Output Voltage (Pin 6 or Pin 9) 10 − Vout − 8.0 − Vpp Differential Output Voltage Swing Capability 10 − Vout − 8.0 − Vpp Power Supply Current I6 +I12 Power Supply Current I14 7 6 ICC IEE − − 2.0 3.0 4.0 5.0 mAdc DC Power Dissipation 7 5 PD − 33 − mW 1. Tlow = 0°C for MC1496 Thigh = +70°C for MC1496 = −40°C for MC1496B = +125°C for MC1496B
Mc1496,Mc1496B GENERAL OPERATING INFORMATION Carrier Feedthrough Note that in the test circuit of Figure 10, Vs corresponds to Carrier feedthrough is defined as the output voltage at a maximum value of 1.0 V peak arrier frequency with only the carrier applied Common Mode Swing Carrier null is achieved by balancing the currents in the The common-mode swing is the voltage which may be (e terential amplifier by means of a bias trim potentiometer applied to both bases of the signal differential amplifier, without saturating the current sources or without saturating the differential amplifier itself by swinging it into the upper Carrier Suppression switching devices. This swing is variable depending on the Carrier suppression is defined as the ratio of each particular circuit and biasing conditions chosen ideband output to carrier output for the carrier and signal voltage levels specified Power Dissipation Carrier suppression is very dependent on carrier input Power dissipation, PD, within the integrated circuit level, as shown in Figure 22. A low value of the carrier does package should be calculated as the summation of the not fully switch the upper switching devices, and results in voltage current products at each port,i.e.assuming lower signal gain, hence lower carrier suppression. A higher than optimum carrier level results in unnecessary device and PD 2 15(V6-V14)+ 15)V5-V14 where subscripts refer circuit carrier feedthrough, which again degenerates the to pin numbers suppression figure. The MC1496 has been characterized Design Equations with a 60 m Vrms sinewave carrier input signal. This level provides optimum carrier suppression at carrier frequencies The following is a partial list of design equations needed in the vicinity of 500 kHz, and is generally recommended for to operate the circuit with other supply voltages and input conditions balanced modulator applications Carrier feedthrough is independent of signal level, V A. Operating Current Thus carrier suppression can be maximized by operating The internal bias currents are set by the conditions at Pin 5 with large signal levels. However, a linear operating mode must be maintained in the signal-input transistor pair-or 15=16=112, harmonics of the modulating signal will be generated and IB<<Ic for all transistors appear in the device output as spurious sidebands of the then suppressed carrier. This requirement places an upper limit optimum carrier level is recommended in Figure 22 for good -15-5002 where: R5 is the resistor between on input-signal amplitude(see Figure 20). Note also that an Pin 5 and ground carrier suppression and minimum spurious sideband φ=075atTA=+25°C generation The MC1496 has been characterized for the condition At higher frequencies circuit layout is very important in 15=1.0 mA and is the generally recommended value order to minimize carrier feedthrough Shielding may be B Common-Mode Quiescent Output Voltage necessary in order to prevent capacitive coupling between V6=V12=V+-15RL the carrier input leads and the output lead Signal Gain and Maximum Input Level Biasing Signal gain(single-ended)at low frequencies is defined The MC1496 requires three dc bias voltage levels which as the voltage gain, must be set externally. Guidelines for setting up these three levels include maintaining at least 2.0 V collector-base bias on all transistors while not exceeding the voltages given in where re the absolute maximum rating table 30vdc≥[(v6,V12)-(V8,v1O≥2Vdc A constant dc potential is applied to the carrier input 30vdc≥[(v8,V10)-(V1,V4)≥2.7vdc terminals to fully switch two of the upper transistors"on 30vdc≥[(v1,V4)-(V5)≥2.7vdc and two transistors"off"(Ve=0.5 Vdc). This in effect The foregoing conditions are based on the following forms a cascode differential amplifier critical value determined by Re and the bias current 5a approximations Linear operation requires that the signal input be below 6=V12,v8=V10,V1=V4 httpllonsemi.com
MC1496, MC1496B http://onsemi.com 4 GENERAL OPERATING INFORMATION Carrier Feedthrough Carrier feedthrough is defined as the output voltage at carrier frequency with only the carrier applied (signal voltage = 0). Carrier null is achieved by balancing the currents in the differential amplifier by means of a bias trim potentiometer (R1 of Figure 5). Carrier Suppression Carrier suppression is defined as the ratio of each sideband output to carrier output for the carrier and signal voltage levels specified. Carrier suppression is very dependent on carrier input level, as shown in Figure 22. A low value of the carrier does not fully switch the upper switching devices, and results in lower signal gain, hence lower carrier suppression. A higher than optimum carrier level results in unnecessary device and circuit carrier feedthrough, which again degenerates the suppression figure. The MC1496 has been characterized with a 60 mVrms sinewave carrier input signal. This level provides optimum carrier suppression at carrier frequencies in the vicinity of 500 kHz, and is generally recommended for balanced modulator applications. Carrier feedthrough is independent of signal level, VS. Thus carrier suppression can be maximized by operating with large signal levels. However, a linear operating mode must be maintained in the signal−input transistor pair − or harmonics of the modulating signal will be generated and appear in the device output as spurious sidebands of the suppressed carrier. This requirement places an upper limit on input−signal amplitude (see Figure 20). Note also that an optimum carrier level is recommended in Figure 22 for good carrier suppression and minimum spurious sideband generation. At higher frequencies circuit layout is very important in order to minimize carrier feedthrough. Shielding may be necessary in order to prevent capacitive coupling between the carrier input leads and the output leads. Signal Gain and Maximum Input Level Signal gain (single−ended) at low frequencies is defined as the voltage gain, AVS Vo VS RL Re2re where re 26 mV I5(mA) A constant dc potential is applied to the carrier input terminals to fully switch two of the upper transistors “on” and two transistors “off” (VC = 0.5 Vdc). This in effect forms a cascode differential amplifier. Linear operation requires that the signal input be below a critical value determined by RE and the bias current I5. VS I5 RE (Volts peak) Note that in the test circuit of Figure 10, VS corresponds to a maximum value of 1.0 V peak. Common Mode Swing The common−mode swing is the voltage which may be applied to both bases of the signal differential amplifier, without saturating the current sources or without saturating the differential amplifier itself by swinging it into the upper switching devices. This swing is variable depending on the particular circuit and biasing conditions chosen. Power Dissipation Power dissipation, PD, within the integrated circuit package should be calculated as the summation of the voltage−current products at each port, i.e. assuming V12 = V6, I5 = I6 = I12 and ignoring base current, PD = 2 I5 (V6 − V14) + I5)V5 − V14 where subscripts refer to pin numbers. Design Equations The following is a partial list of design equations needed to operate the circuit with other supply voltages and input conditions. A. Operating Current The internal bias currents are set by the conditions at Pin 5. Assume: I5 = I6 = I12, IBIC for all transistors then : R5V I5 500 where: R5 is the resistor between where: Pin 5 and ground where: = 0.75 at TA = +25°C The MC1496 has been characterized for the condition I5 = 1.0 mA and is the generally recommended value. B. Common−Mode Quiescent Output Voltage V6 = V12 = V+ − I5 RL Biasing The MC1496 requires three dc bias voltage levels which must be set externally. Guidelines for setting up these three levels include maintaining at least 2.0 V collector−base bias on all transistors while not exceeding the voltages given in the absolute maximum rating table; 30 Vdc [(V6, V12) − (V8, V10)] 2 Vdc 30 Vdc [(V8, V10) − (V1, V4)] 2.7 Vdc 30 Vdc [(V1, V4) − (V5)] 2.7 Vdc The foregoing conditions are based on the following approximations: V6 = V12, V8 = V10, V1 = V4
Mc1496,Mc1496B Bias currents flowing into Pins 1. 4. 8 and 10 are transistor base currents and can normally be neglected if external bias VEE Should be dc only. The insertion of an RF choke in dividers are designed to carry 1.0 ma or more series with Vee can enhance the stability of the internal current sources Transadmittance Bandwidth Carrier transadmittance bandwidth is the 3.0 dB bandwidth Signal Port Stability of the device forward transadmittance as defined by Under certain values of driving source impedance Y21C<o(each sideband) oscillation may occur. In this event, an RC suppression Vo=0 network should be connected directly to each input using hort leads. This will reduce the Q of the source-tuned Signal transadmittance bandwidth is the 3.0 dB bandwidth circuits that cause the oscillation of the device forward transadmittance as defined by (signal) Y21Sv(signal Ivc=0.5 Vdc, Vo=o (Pins 1 and 4) Coupling and Bypass Capacitors Capacitors CI and C2 (Figure 5)should be selected for a reactance of less than 5.0 $2 at the carrier frequency An alternate method for low-frequency applications is to Output signal insert a 1.0 k9 resistor in series with the input(Pins 1, 4). In The output signal is taken from Pins 6 and 12 either this case input current drift may cause serious degradation balanced or single-ended Figure lI shows the output levels of carrier suppression of each of the two output sidebands resulting from variations in both the carrier and modulating signal inputs with a single-ended output connection TEST CIRCUITS 12 Vdc 1.0k Re=1.0k 0.1uF T Carrier 0.1 uF Mc1496 Zina MC1496 14 10k10k5 14 1568k Carrier nul -8.0 Vdc Figure 5. Carrier Rejection and Suppression Figure 6. Input-Output Impedance 10k 12 Vdc .0k 01证木 20k Carrier 1.0k Mc1496 Mc14966 Modulating 14 50k Carrier null 8.0 Vdc -8.0 Vdc VEE Figure 7. Bias and Offset Currents Figure 8. Transconductance Bandwidth httpllonsemi.com
MC1496, MC1496B http://onsemi.com 5 Bias currents flowing into Pins 1, 4, 8 and 10 are transistor base currents and can normally be neglected if external bias dividers are designed to carry 1.0 mA or more. Transadmittance Bandwidth Carrier transadmittance bandwidth is the 3.0 dB bandwidth of the device forward transadmittance as defined by: 21C i o (each sideband) vs (signal) Vo 0 Signal transadmittance bandwidth is the 3.0 dB bandwidth of the device forward transadmittance as defined by: 21S i o (signal) vs (signal) Vc 0.5 Vdc, Vo 0 Coupling and Bypass Capacitors Capacitors C1 and C2 (Figure 5) should be selected for a reactance of less than 5.0 at the carrier frequency. Output Signal The output signal is taken from Pins 6 and 12 either balanced or single−ended. Figure 11 shows the output levels of each of the two output sidebands resulting from variations in both the carrier and modulating signal inputs with a single−ended output connection. Negative Supply VEE should be dc only. The insertion of an RF choke in series with VEE can enhance the stability of the internal current sources. Signal Port Stability Under certain values of driving source impedance, oscillation may occur. In this event, an RC suppression network should be connected directly to each input using short leads. This will reduce the Q of the source−tuned circuits that cause the oscillation. Signal Input (Pins 1 and 4) 510 10 pF An alternate method for low−frequency applications is to insert a 1.0 k resistor in series with the input (Pins 1, 4). In this case input current drift may cause serious degradation of carrier suppression. NOTE: Shielding of input and output leads may be needed to properly perform these tests. Figure 5. Carrier Rejection and Suppression Figure 6. Input−Output Impedance Figure 7. Bias and Offset Currents Figure 8. Transconductance Bandwidth 0.01 F 2.0 k −8.0 Vdc I6 I9 1.0 k I7 I8 6.8 k Zout +Vo + +Vo I9 3 RL 3.9 k VCC 12 Vdc 8 C1 0.1 F MC1496 1.0 k 2 Re 1.0 k C2 0.1 F 51 10 k Modulating Signal Input Carrier InputVC Carrier Null 10 k 51 51 50 k R1 VS −Vo RL 3.9 k I6 I4 6 14 5 12 − 2 Re = 1.0 k 3 Zin 0.5 V 8 10 I1 4 1 10 −Vo 1 6 4 14 5 12 6.8 k V− I10 I5 −8.0 Vdc VEE 1.0 k MC1496 MC1496 6 MC1496 14 5 12 I10 6.8 k −8.0 Vdc VEE VCC 12 Vdc 2 Re = 1.0 k 3 1.0 k Modulating Signal Input Carrier Input VC VS 0.1 F 0.1 F 1.0 k 51 1.0 k 14 5 6 12 1.0 k 2 3 Re VCC 12 Vdc 2.0 k +Vo −Vo 6.8 k 10 k Carrier Null 10 k 51 50 k V− −8.0 Vdc VEE 50 50 8 10 4 1 8 10 4 1 51 TEST CIRCUITS