《电子工程师手册》学习资料（英文版）Memory devices 80

Pricer, W.D., Katz, R.H., Lee, P.A., Mansuripur, M. Memory Devices The Electrical Engineering Handbook Ed. Richard C. Dorf Boca raton crc Press llc. 2000

Pricer, W.D., Katz, R.H., Lee, P.A., Mansuripur, M. “Memory Devices” The Electrical Engineering Handbook Ed. Richard C. Dorf Boca Raton: CRC Press LLC, 2000

80 Memory devices 0.1 Integrated Circuits(RAM, ROM Dynamic RAMs(DRAMs). Static RAMs(SRAMs). Nonvolatile Programmable Memories.Read-Only Memories(ROMs W. David pricer 0.2 Basic Disk system architectures Basic Magnetic Disk System Architecture. Characterization of 1yo Randy h. Katz Workloads. Extensions to Conventional Disk Architectures University of california, Berkeley 80.3 Magnet A Brief Historical Review. Introduction. Magnetic Tape. Tape Peter A. Lee Format. Recording Modes Department of Trade and Industry 80.4 Magneto-Optical Disk Data Storage Preliminaries and Basic Definitions. The Optical Path. Automatic Focusing. Automatic Tracking Thermomagnetic Recording M. Mansuripur Process. Magneto-Optical Readout. Materials of Magneto-Optical University of Arizona, Tucson Data Storage 80.1 Integrated Circuits(RAM, ROM) W. David pricer The major forms of semiconduct ding order of present economic importance are 1. Dynamic Random-Access Memories(DRAMs) 2. Static Random-Access Memories(SRAMs) 3. Nonvolatile Programmable Memories(PROMs, EEPROMS, EAROMS, EPROMs) 4. Read-Only Memories(ROMs) DRAMs and SRAMs differ little in their applications. DRAMs are distinguished from SRAMs in that no bistable electronic circuit internal to the storage cell maintains the information. Instead DRAM information is stored"dynamically"as charge on a capacitor. All modern designs feature one field-effect transistor(FET)to access the information for both reading and writing and a thin film capacitor for information storage. SRAMs maintain their bistability, so long as power is applied, by a cross-coupled pair of inverters within each storage cell. Almost always two additional transistors serve to access the internal nodes for reading and writing. Most modern cell designs are CMOS, with two P-channel and four N-channel FETs Programmable memories operate much like read-only memories with the important attribute that they can be programmed at least once, and some can be reprogrammed a million times or more. Storage is almost always by means of a floating-gate FET. Information in such storage cells is not indefinitely nonvolatile. The discharge time constant is on the order of ten years. ROMs are generally programmed by a custom information mask within the fabrication sequence. As the name implies, information thence can only be read. The inf thus stored is truly nonvolatile, even when power is removed. This is the most dense form of semiconductor storage(and the least flexible). Other forms of semiconductor memories, such as associative memories and arge-coupled devices, are used rarely. c 2000 by CRC Press LLC

© 2000 by CRC Press LLC 80 Memory Devices 80.1 Integrated Circuits (RAM, ROM) Dynamic RAMs (DRAMs) • Static RAMs (SRAMs) • Nonvolatile Programmable Memories • Read-Only Memories (ROMs) 80.2 Basic Disk System Architectures Basic Magnetic Disk System Architecture • Characterization of I/O Workloads • Extensions to Conventional Disk Architectures 80.3 Magnetic Tape A Brief Historical Review • Introduction • Magnetic Tape • Tape Format • Recording Modes 80.4 Magneto-Optical Disk Data Storage Preliminaries and Basic Definitions • The Optical Path • Automatic Focusing • Automatic Tracking • Thermomagnetic Recording Process • Magneto-Optical Readout • Materials of Magneto-Optical Data Storage 80.1 Integrated Circuits (RAM, ROM) W. David Pricer The major forms of semiconductor memory in descending order of present economic importance are 1. Dynamic Random-Access Memories (DRAMs) 2. Static Random-Access Memories (SRAMs) 3. Nonvolatile Programmable Memories (PROMs, EEPROMs, EAROMs, EPROMs) 4. Read-Only Memories (ROMs) DRAMs and SRAMs differ little in their applications. DRAMs are distinguished from SRAMs in that no bistable electronic circuit internal to the storage cell maintains the information. Instead DRAM information is stored “dynamically” as charge on a capacitor. All modern designs feature one field-effect transistor (FET) to access the information for both reading and writing and a thin film capacitor for information storage. SRAMs maintain their bistability, so long as power is applied, by a cross-coupled pair of inverters within each storage cell. Almost always two additional transistors serve to access the internal nodes for reading and writing. Most modern cell designs are CMOS, with two P-channel and four N-channel FETs. Programmable memories operate much like read-only memories with the important attribute that they can be programmed at least once, and some can be reprogrammed a million times or more. Storage is almost always by means of a floating-gate FET. Information in such storage cells is not indefinitely nonvolatile. The discharge time constant is on the order of ten years. ROMs are generally programmed by a custom information mask within the fabrication sequence. As the name implies, information thence can only be read. The information thus stored is truly nonvolatile, even when power is removed. This is the most dense form of semiconductor storage (and the least flexible). Other forms of semiconductor memories, such as associative memories and charge-coupled devices, are used rarely. W. David Pricer IBM Randy H. Katz University of California, Berkeley Peter A. Lee Department of Trade and Industry, London M. Mansuripur University of Arizona, Tucson

Dynamic RAMs(DRAMs The universally used storage cell circuit of one transistor and one capacitor has remained unchanged for over 20 years. The physical implementation, however, has undergone much diversity and many refinements. The innovation in physical nplementation is driven primarily by the need to maintain a nearly constant value of capacitance while the surface area of the cell has decreased. A nearly fixed value of capacitance is needed to meet two important design goals. The cell has no internal amplification. Once the information is accessed, the stored voltage is vastly attenuated by the much larger bit line capacitance(see Fig. 80. 1). The resulting signal must be kept arger than the resolution limits of the sensing amplifier. DRAMs in particular are also sensitive to a problem called soft errors. These are typically initiated by atomic events such as the incidence of a single alpha particle. An alpha particle can ourious signal of 50,000 electrons or more. All mod- FIGURE 80.1 Cell and bit line capacitance. ern dRAm designs resolve this problem by constructing the capacitor in space out of the plane of the transistors(see Fig 80.2 for examples). Placing the capacitor in space unusable for transistor fabrication has allowed great strides in DRAM density, generally at the expense of fabrication complexity. DRAM chip capacity has increased by about a factor of four every three years. RAMs are somewhat slower than SRAMs. This relationship derives directly from the smaller signal ava from DRAMs and from certain constraints put on the support circuitry by the DRAM array. DRaM Word line Capacitor dielectric layer Insulating layer Electrode 2(Cell plate Isolation Electrode-1(Storage electrode 691815kvxi:"3:的 层 FIGURE 80.2 (a)Cross section of "trench capacitors"etched vertically into the semiconductor surface of a DRAM inte- grated circuit. (Courtesy of IBM. )(b)Cross section of"stacked"capacitors fabricated above the semiconductor surface of a DRAM integrated circuit. ( Source: M. Taguchi et al., "A 40-ns 64-b parallel data bus architecture, IEEE J. Solid State Circuits, voL. 26, no. 11, P. 1495. e 1991 IEEE. With permission. e 2000 by CRC Press LLC

© 2000 by CRC Press LLC Dynamic RAMs (DRAMs) The universally used storage cell circuit of one transistor and one capacitor has remained unchanged for over 20 years. The physical implementation, however, has undergone much diversity and many refinements. The innovation in physical implementation is driven primarily by the need to maintain a nearly constant value of capacitance while the surface area of the cell has decreased. A nearly fixed value of capacitance is needed to meet two important design goals. The cell has no internal amplification. Once the information is accessed, the stored voltage is vastly attenuated by the much larger bit line capacitance (see Fig. 80.1). The resulting signal must be kept larger than the resolution limits of the sensing amplifier. DRAMs in particular are also sensitive to a problem called soft errors. These are typically initiated by atomic events such as the incidence of a single alpha particle. An alpha particle can cause a spurious signal of 50,000 electrons or more. All mod￾ern DRAM designs resolve this problem by constructing the capacitor in space out of the plane of the transistors (see Fig. 80.2 for examples). Placing the capacitor in space unusable for transistor fabrication has allowed great strides in DRAM density, generally at the expense of fabrication complexity. DRAM chip capacity has increased by about a factor of four every three years. DRAMs are somewhat slower than SRAMs. This relationship derives directly from the smaller signal available from DRAMs and from certain constraints put on the support circuitry by the DRAM array. DRAMs also FIGURE 80.2 (a) Cross section of “trench capacitors” etched vertically into the semiconductor surface of a DRAM inte￾grated circuit. (Courtesy of IBM.) (b) Cross section of “stacked” capacitors fabricated above the semiconductor surface of a DRAM integrated circuit. (Source: M. Taguchi et al., “A 40-ns 64-b parallel data bus architecture,” IEEE J. Solid State Circuits, vol. 26, no. 11, p. 1495. © 1991 IEEE. With permission.) FIGURE 80.1 Cell and bit line capacitance

THE REVOLUTION OF ELECTRONICS TECHNOLOGY he last three decades have witnessed a revo- lution in electrical and, especially, electron technology. This revolution was paced by changes in solid-state electronics that greatly expanded capabilities while at the same time ally reduced costs. The entire field of electrical en neering has grown far beyond the boundaries that characterized it just a generation ago. Electrical neers have become the creators and masters of the most pervasive technology of our time, with pro- found effects on society and on their profession The effects of the electronics revolution are com plex. For the profession, the most obvious impact has been explosive growth. The increase in the num- ber of students studying in the field continues to be dramatic and shows no signs of slowing. The elec- trical engineering community represents the largest This 64-kB random access memory chip, developed single technical group in the world, and the mem- by IBM in 1978, was one of the densest of its time. It bers of the IEEE make up the worlds largest engi- could store as many as 64,000 bits of informa neering society.( Courtesy of the IEEE Center for th tion-roughly equivalent to 1, 000 eight-letter words. History of Electrical Engineering (Photo courtesy of the IEEE Center for the History of Electrical Engineering. require periodic intervals to"refresh"lost charge from the capacitor. This charge is lost primarily across the emiconductor junctions and must be replenished every few milliseconds. The manufacturer usually supplies hese"housekeeping, " functions with on-chip circuitry. Signal detection and amplification remain a critical focus of good DRAM design. Figure 80.3 illustrates an arrangement called a"folded bit line. This design cancels many of the noise sources originating in the array and decreases circuit sensitivity to manufacturing process variations. It also achieves a high ratio of storage cells per sense amplifier. Note the presence of the dummy cells, which create a reference signal midway between one"and a"zero"for the convenience of the sense amplifier. The stored reference voltage in this case is two driven bit lines afte lls has been written Large DRAM integrated circuit chips frequently provide other features that users may find useful. access is provided between certain adjacent addresses, usually along a common word line. Some designs on-chip buffer memories, low standby power modes, or error correction circuitry. A few DRAM chips designed to mesh with the constraints of particular applications such as image support for CRT displays. Some on-chip features are effectively hidden from the user. These include redunda nt memory addresses which the maker activates by laser to improve manufacturing yield. The largest single market for DRAMs is with microprocessors in personal computers. Rapid microprocessor performance improvements have led DRAM manufacturers to offer improvements especially designed for the PC environment. Extended Data Out mode(EDO) keeps the data accessed from a DRAM valid over a longer period of the DRAM cycle. EDO mode is intended to ease the synchronization problem between a DRAM and the increasingly higher speed microprocessor. Synchronous DRAM(SDRAM)allows the rapid sequential e 2000 by CRC Press LLC

© 2000 by CRC Press LLC require periodic intervals to “refresh” lost charge from the capacitor. This charge is lost primarily across the semiconductor junctions and must be replenished every few milliseconds. The manufacturer usually supplies these “housekeeping” functions with on-chip circuitry. Signal detection and amplification remain a critical focus of good DRAM design. Figure 80.3 illustrates an arrangement called a “folded bit line.” This design cancels many of the noise sources originating in the array and decreases circuit sensitivity to manufacturing process variations. It also achieves a high ratio of storage cells per sense amplifier. Note the presence of the dummy cells, which create a reference signal midway between a “one” and a “zero” for the convenience of the sense amplifier. The stored reference voltage in this case is created by shorting two driven bit lines after one of the storage cells has been written. Large DRAM integrated circuit chips frequently provide other features that users may find useful. Faster access is provided between certain adjacent addresses, usually along a common word line. Some designs feature on-chip buffer memories, low standby power modes, or error correction circuitry. A few DRAM chips are designed to mesh with the constraints of particular applications such as image support for CRT displays. Some on-chip features are effectively hidden from the user. These may include redundant memory addresses which the maker activates by laser to improve manufacturing yield. The largest single market for DRAMs is with microprocessors in personal computers. Rapid microprocessor performance improvements have led DRAM manufacturers to offer improvements especially designed for the “PC” environment. Extended Data Out mode (EDO) keeps the data accessed from a DRAM valid over a longer period of the DRAM cycle. EDO mode is intended to ease the synchronization problem between a DRAM and the increasingly higher speed microprocessor. Synchronous DRAM (SDRAM) allows the rapid sequential THE REVOLUTION OF ELECTRONICS TECHNOLOGY he last three decades have witnessed a revo￾lution in electrical and, especially, electron￾ics technology. This revolution was paced by changes in solid-state electronics that greatly expanded capabilities while at the same time radi￾cally reduced costs. The entire field of electrical engi￾neering has grown far beyond the boundaries that characterized it just a generation ago. Electrical engi￾neers have become the creators and masters of the most pervasive technology of our time, with pro￾found effects on society and on their profession. The effects of the electronics revolution are com￾plex. For the profession, the most obvious impact has been explosive growth. The increase in the num￾ber of students studying in the field continues to be dramatic and shows no signs of slowing. The elec￾trical engineering community represents the largest single technical group in the world, and the mem￾bers of the IEEE make up the world’s largest engi￾neering society. (Courtesy of the IEEE Center for the History of Electrical Engineering.) This 64-kB random access memory chip, developed by IBM in 1978, was one of the densest of its time. It could store as many as 64,000 bits of informa￾tion—roughly equivalent to 1,000 eight-letter words. (Photo courtesy of the IEEE Center for the History of Electrical Engineering.) T

MULTICOORDINATE DIGITAL INFORMATION STORAGE DEVICE Jay w. For rrester Patented February 28, 1956 #2,736,880 p to this time, digital data storage was generally done by encoding binary data on rotating magnetic drums or other means where data had to be stored and retrieved sequentially. This patent describes a syste whereby data could be stored and retrieved domly by a simple addressing scheme. It used tiny doughnut-shaped ferromagnetic cores with windings to magnetically polarize the material in one direction or the other. This was about one hundred times faster than rotating drums nd took up perhaps 2% of the volume. A Fig. 2 4-Kbyte core memory module would take up about 60 cubic inches and could access data in less than one millisecond. Random access mem- ory(rAm) was born. Core memory(as it has become known) was non-volatile; that is, the information would not be lost when power was cut. Modern non-volatile"flash" memory is yet again thousands of times faster and achieves data density of over 100,000 times greater than the breakthrough magnetic core memory described by Forrester.( Copyright o 1 DewRay Products, Inc. Used with permission. transfer of large blocks of data between the microprocessor and the DRAM without extensive signal"hand shaking". While SDRAMs do nothing to improve the access time to first data, they greatly improve the "band width"between microprocessor and DRAM Static RAMs(SRAMs The primary advantages of SRAMs as compared to DRAMs are high speed and ease of use. In addition, SRAMs fabricated in CMOS technology exhibit extremely low standby power. This later feature is effectively used in much portable equipment like pocket calculators. Bipolar SRAMs are generally faster but less dense than FEt versions. Figure 80.4 illustrates two cells. SRAM performance is dominated by the speed of the support circuits leading some manufacturers to design bipolar support circuits to FET arrays Bipolar designs frequently incorporate circuit consolidation unavailable in FET technology, such as the multi emitter cell shown in Fig. 80.4(a). Here one of the two lower emitters is normally forward biased, turning one inverter on and the other off for bistability. The upper emitters can be used either to extract a differential signal e 2000 by CRC Press LLC

© 2000 by CRC Press LLC transfer of large blocks of data between the microprocessor and the DRAM without extensive signal “hand￾shaking”. While SDRAMs do nothing to improve the access time to first data, they greatly improve the “band￾width” between microprocessor and DRAM. Static RAMs (SRAMs) The primary advantages of SRAMs as compared to DRAMs are high speed and ease of use. In addition, SRAMs fabricated in CMOS technology exhibit extremely low standby power. This later feature is effectively used in much portable equipment like pocket calculators. Bipolar SRAMs are generally faster but less dense than FET versions. Figure 80.4 illustrates two cells. SRAM performance is dominated by the speed of the support circuits, leading some manufacturers to design bipolar support circuits to FET arrays. Bipolar designs frequently incorporate circuit consolidation unavailable in FET technology, such as the multi￾emitter cell shown in Fig. 80.4(a). Here one of the two lower emitters is normally forward biased, turning one inverter on and the other off for bistability. The upper emitters can be used either to extract a differential signal MULTICOORDINATE DIGITAL INFORMATION STORAGE DEVICE Jay W. Forrester Patented February 28, 1956 #2,736,880 p to this time, digital data storage was generally done by encoding binary data on rotating magnetic drums or other means where data had to be stored and retrieved sequentially. This patent describes a system whereby data could be stored and retrieved ran￾domly by a simple addressing scheme. It used tiny doughnut-shaped ferromagnetic cores with windings to magnetically polarize the material in one direction or the other. This was about one hundred times faster than rotating drums and took up perhaps 2% of the volume. A 4-Kbyte core memory module would take up about 60 cubic inches and could access data in less than one millisecond. Random access mem￾ory (RAM) was born. Core memory (as it has become known) was non-volatile; that is, the information would not be lost when power was cut. Modern non-volatile “flash” memory is yet again thousands of times faster and achieves data density of over 100,000 times greater than the breakthrough magnetic core memory described by Forrester. (Copyright © 1995, DewRay Products, Inc. Used with permission.) U