FIGURE 80.3 Folded bit line array. Word Line Word Line FIGURE 80.4(a) Bipolar SRAM cell.(b) CMOS SRAM cell. or to discharge one collector towards ground in order to write the cell. The word line is pulsed positive to both ead and write the cell a A few RAMs use polysilicon load resistors of very high resistance value in place of the two P-channel transistors are constructed by thin film techniques and are physically placed over the N-channel transistors to aprove density. When both P-and N-channel transistors are fabricated in the same plane of the single-crystal semiconductor, the standby current can be extremely low. Typically this can be microamps for megabit chips The low standby current is possible because each cell sources and sinks only that current needed to overcome the actual node leakage within the cell Selecting the proper transconductance for each transistor is an important focus of the designer. The accessing transistors should be large enough to extract a large read signal but insufficiently large to disturb the stored information. During the write operation, these same transistors must be capable of overriding the current drive of at least one of the internal cmos inverters The superior performance of SRAMs derives from their larger signal and the absence of a need to refresh the stored information as in a DRAM. As a result, SRAMs need fewer sense amplifiers. Likewise these amplifiers are not constrained to match the cell pitch of the array. sram design engineers have exploited this freedom to realize higher-performance sense amplifiers e 2000 by CRC Press LLC
© 2000 by CRC Press LLC or to discharge one collector towards ground in order to write the cell. The word line is pulsed positive to both read and write the cell. A few RAMs use polysilicon load resistors of very high resistance value in place of the two P-channel transistors shown in Fig. 80.4(b). Most are full CMOS designs like the one shown. Sometimes the P-channel transistors are constructed by thin film techniques and are physically placed over the N-channel transistors to improve density. When both P- and N-channel transistors are fabricated in the same plane of the single-crystal semiconductor, the standby current can be extremely low. Typically this can be microamps for megabit chips. The low standby current is possible because each cell sources and sinks only that current needed to overcome the actual node leakage within the cell. Selecting the proper transconductance for each transistor is an important focus of the designer. The accessing transistors should be large enough to extract a large read signal but insufficiently large to disturb the stored information. During the write operation, these same transistors must be capable of overriding the current drive of at least one of the internal CMOS inverters. The superior performance of SRAMs derives from their larger signal and the absence of a need to refresh the stored information as in a DRAM. As a result, SRAMs need fewer sense amplifiers. Likewise these amplifiers are not constrained to match the cell pitch of the array. SRAM design engineers have exploited this freedom to realize higher-performance sense amplifiers. FIGURE 80.3 Folded bit line array. FIGURE 80.4 (a) Bipolar SRAM cell. (b) CMOS SRAM cell
Practical SRAM designs routinely achieve access times of a few nanoseconds to a few tens of nanoseconds. Cycle time typically equals access time, and in at least one pipelined design, cycle time is actually less than access time SRAM integrated circuit chips have fewer special on-chip features than DRAM chips, primarily because no special performance enhancements are needed. By contrast, many other integrated circuit chips feature on- hip SRAMs. For example, many ASICs(application-specific integrated circuits) feature on-chip RAMs because of their low power and ease of use. k between processor and memory. Nonvolatile programmable memories A few nonvolatile memories are programmable just once. These have arrays of diodes or transistors with fuses or antifuse in series with platinum silicide, and polysilicon have all beene itanium, tungsten, successfully used as fuse technology (see Fig. 80.5 Most nonvolatile cells rely on trapped charge stored on a floa gate in an FET. These can be rewritten many times. The trapped charge is subject to very long term leakage, on the order of ten years. The number of times the cell may be rewritten is limited by pro gramming stress-induced degradation of the dielectric. Charge LIne eling or by avalanche tion from a region near the drain. Both phenomena are induced by over-voltage conditions and hence the degradation after repeated erase/write cycles. Commercially available chips typically promise 100 to 100,000 write cycles. Erasure of charge from the floating gate Word may be by tunneling or by exposure to ultraviolet light. Asperities on the polysilicon gate and silicon-rich oxide have both been shown enhance charging and discharging of the gate. The nomenclature sed is not entirely consistent throughout the industry. Ho EPROM is generally used to describe cells which are electronically written but uV erased. eeprom is used to describe cells which are electronically both written and erased. Cells are of either a two-or a one-transistor design. where two transistors are used. the second transistor is a conventional enhance- ment mode transistor(see Fig 80.6). The second transistor works FIGURE 80.5 PROM cells the disturb of unselected cells. it al constraints on the writing limits of the programmable transistor, which in one state may be depletion mode The two transistors in series then assume the threshold of the second(enhancement)transistor, or a very high threshold as determined by the programmable transistor. Some designs are so cleverly integrated that the features of the two transistors are merged Flash EEPROMs describe a family of single-transistor cell EPPROMs. Cell sizes are about half that of two- transistor EEPROMs, an important economic consideration. Care must be taken that these re not programmed into the depletion mode. An array of depletion mode cells would confound the read operation by providing multiple signal paths. Programming to enhancement only thresholds can be accomplished by a sequence of partial program and then monitor subcycles, until the threshold is brought to compliance with tion limits. Flash EEPROMs require bulk erasure of large portions of the array nvrAM is a term used to describe a sram or dram with nonvolatile circuit elements the cell is built to operate as a RAM with normal power applied On command or with power failure imminent, the EEPROM elements can be activated to capture the last state of the RAM cell. The nonvolatile information is restored to SRAM cell by normal internal cell regeneration when power is restored e 2000 by CRC Press LLC
© 2000 by CRC Press LLC Practical SRAM designs routinely achieve access times of a few nanoseconds to a few tens of nanoseconds. Cycle time typically equals access time, and in at least one pipelined design, cycle time is actually less than access time. SRAM integrated circuit chips have fewer special on-chip features than DRAM chips, primarily because no special performance enhancements are needed. By contrast, many other integrated circuit chips feature onchip SRAMs. For example, many ASICs (application-specific integrated circuits) feature on-chip RAMs because of their low power and ease of use. All modern microprocessors include one or more on-chip “cache” SRAM memories which provide a high speed link between processor and memory. Nonvolatile Programmable Memories A few nonvolatile memories are programmable just once. These have arrays of diodes or transistors with fuses or antifuses in series with each semiconductor cross point. Aluminum, titanium, tungsten, platinum silicide, and polysilicon have all been successfully used as fuse technology (see Fig. 80.5). Most nonvolatile cells rely on trapped charge stored on a floating gate in an FET. These can be rewritten many times. The trapped charge is subject to very long term leakage, on the order of ten years. The number of times the cell may be rewritten is limited by programming stress-induced degradation of the dielectric. Charge reaches the floating gate either by tunneling or by avalanche injection from a region near the drain. Both phenomena are induced by over-voltage conditions and hence the degradation after repeated erase/write cycles. Commercially available chips typically promise 100 to 100,000 write cycles. Erasure of charge from the floating gate may be by tunneling or by exposure to ultraviolet light. Asperities on the polysilicon gate and silicon-rich oxide have both been shown to enhance charging and discharging of the gate. The nomenclature used is not entirely consistent throughout the industry. However, EPROM is generally used to describe cells which are electronically written but UV erased. EEPROM is used to describe cells which are electronically both written and erased. Cells are of either a two- or a one-transistor design. Where two transistors are used, the second transistor is a conventional enhancement mode transistor (see Fig. 80.6). The second transistor works to minimize the disturb of unselected cells. It also removes some constraints on the writing limits of the programmable transistor, which in one state may be depletion mode. The two transistors in series then assume the threshold of the second (enhancement) transistor, or a very high threshold as determined by the programmable transistor. Some designs are so cleverly integrated that the features of the two transistors are merged. Flash EEPROMs describe a family of single-transistor cell EPPROMs. Cell sizes are about half that of twotransistor EEPROMs, an important economic consideration. Care must be taken that these cells are not programmed into the depletion mode. An array of depletion mode cells would confound the read operation by providing multiple signal paths. Programming to enhancement only thresholds can be accomplished by a sequence of partial program and then monitor subcycles, until the threshold is brought to compliance with specification limits. Flash EEPROMs require bulk erasure of large portions of the array. NVRAM is a term used to describe a SRAM or DRAM with nonvolatile circuit elements. The cell is built to operate as a RAM with normal power applied. On command or with power failure imminent, the EEPROM elements can be activated to capture the last state of the RAM cell. The nonvolatile information is restored to a SRAM cell by normal internal cell regeneration when power is restored. FIGURE 80.5 PROM cells
Control Gate Floating Gate ection Gate Floating Gate Enhancement Mode Diffusion Transistor Transistor FIGURE 80.6 Cross section of two-transistor EEPROM cells Read-Only Memories(ROMs) ROMs are the only form of semiconductor storage which is permanently nonvolatile. Information is retained without Word LIne power applied, and there is not even very gradual informa tion loss as in eeproms. it is also the most dense form of semiconductor storage. ROMs are, however, less used than RAMs or EEPROMs. ROMs must be personalized by a mask Mask in the fabrication process. This method is cumbersome and expensive unless many identical parts are to be made. Fur- Programmable thermore it seems much"permanent"information is not ally permanent and must be occasionally updated. Bit Line ROM cells can be formed as diodes or transistors at every intersection of the word and bit lines of a ROm array(see FIGURE 80.7 ROM cell Fig. 80.7). One of the masks in the chip fabrication process programs which of these devices will be active Clever layout and circuit techniques may be used to obtain further density. Two such techniques are illustrated in Figs. 80.8 and 80.9. The X array shares bit and virtual ground lines. The AND array places many ROM cells in series. Each of these series AND ROM cells is either Contacts to a FIGURE 80.8 Layout of ROS X array. e 2000 by CRC Press LLC
© 2000 by CRC Press LLC Read-Only Memories (ROMs) ROMs are the only form of semiconductor storage which is permanently nonvolatile. Information is retained without power applied, and there is not even very gradual information loss as in EEPROMs. It is also the most dense form of semiconductor storage. ROMs are, however, less used than RAMs or EEPROMs. ROMs must be personalized by a mask in the fabrication process. This method is cumbersome and expensive unless many identical parts are to be made. Furthermore it seems much “permanent” information is not really permanent and must be occasionally updated. ROM cells can be formed as diodes or transistors at every intersection of the word and bit lines of a ROM array (see Fig. 80.7). One of the masks in the chip fabrication process programs which of these devices will be active. Clever layout and circuit techniques may be used to obtain further density. Two such techniques are illustrated in Figs. 80.8 and 80.9. The X array shares bit and virtual ground lines. The AND array places many ROM cells in series. Each of these series AND ROM cells is either FIGURE 80.6 Cross section of two-transistor EEPROM cells. FIGURE 80.8 Layout of ROS X array. FIGURE 80.7 ROM cell
Gate 下m ROS Oxide Isolation FIGURE 80.9 Layout of ROS AND arra n enhancement or a depletion channel of an FET Sensing is accomplished by pulsing the gates of all series cells positive except the gate which is to be interrogated. Current will flow through all series channels only if the interrogated channel is depletion mode. ROM applications include look-up tables, machine-level instruction code for computers, and small array used to perform logic(see PLA in Section 81.4 of this handbook) Defining Terms Antifuse: A fuse-like device which when activated becomes low impedance. Application-specific integrated circuits(ASICs): Integrated circuits specifically designed for one particular Avalanche injection: The physics whereby electrons highly energized in avalanche current at a semiconductor junction can penetrate into a dielectric. Depletion mode: An FET which is on when zero volts bias is applied from gate to source. Enhancement mode: An fet which is off whe zero vo lts bias is applied from gate to source. Polysilicon: Silicon in polycrystalline form. Tunneling: A physical phenomenon whereby an electron can move instantly through a thin dielectric. Related Topic d References H Kalter et al., "A 50 nsec 16 Mb DRAM with 10 nsec data rate and on-chip ECC, IEEE Journal of Solid-State Circuits, vol. SC 25, no 5, 1990 H Kato, A 9 nsec 4 Mb BiCMOS SRAM with 3.3 V operation, Digest of Technical Papers ISSCC, vol 35, 1992 H. Kawague, and N. Tsuji, Minimum size ROM structure compatible with silicon-gate E/D MOS LSI, IEEE Journal of Solid State Circuits, vol. SC 11, no. 2, 1976 Further Information W. Donoghue et al., "A 256K H CMOS ROM using a four state cell approach, IEEE Journal of Solid-State Circuits, vol SC20, no 2, 1985 e 2000 by CRC Press LLC
© 2000 by CRC Press LLC an enhancement or a depletion channel of an FET. Sensing is accomplished by pulsing the gates of all series cells positive except the gate which is to be interrogated. Current will flow through all series channels only if the interrogated channel is depletion mode. ROM applications include look-up tables, machine-level instruction code for computers, and small arrays used to perform logic (see PLA in Section 81.4 of this handbook). Defining Terms Antifuse: A fuse-like device which when activated becomes low impedance. Application-specific integrated circuits (ASICs): Integrated circuits specifically designed for one particular application. Avalanche injection: The physics whereby electrons highly energized in avalanche current at a semiconductor junction can penetrate into a dielectric. Depletion mode: An FET which is on when zero volts bias is applied from gate to source. Enhancement mode: An FET which is off when zero volts bias is applied from gate to source. Polysilicon: Silicon in polycrystalline form. Tunneling: A physical phenomenon whereby an electron can move instantly through a thin dielectric. Related Topic 25.3 Application-Specific Integrated Circuits References H. Kalter et al., “A 50 nsec 16 Mb DRAM with 10 nsec data rate and on-chip ECC,” IEEE Journal of Solid-State Circuits, vol. SC 25, no. 5, 1990. H. Kato, “A 9 nsec 4 Mb BiCMOS SRAM with 3.3 V operation,” Digest of Technical Papers ISSCC, vol 35, 1992. H. Kawague, and N. Tsuji, “Minimum size ROM structure compatible with silicon-gate E/D MOS LSI,” IEEE Journal of Solid State Circuits, vol. SC 11, no. 2, 1976. Further Information W. Donoghue et al., “A 256K H CMOS ROM using a four state cell approach,” IEEE Journal of Solid-State Circuits, vol. SC20, no. 2, 1985. FIGURE 80.9 Layout of ROS AND array
D. Frohmann-Bentchkowsky, "A fully decoded 2048 bit electronically programmable MOS-ROM, Digest of Technical Papers ISSCC, vol. 14, 1971 L. A Glasser and D. W. Dobberpuhl, The Design and Analysis of VLSI Circuits, Reading, Mass. Addison-Wesle 1985 F Masuoka, Are you ready of the next generation dynamic RAM chips, IEEE Spectrum Magazine, vol. 27, no 19 R. D. Pashley and S. K. Lai, Flash memories: The best of two worlds, " IEEE Spectrum Magazine, vol 26,no 12,1989. 2 Basic disk System Architectures Randy h. Katz Architects of high-performance computers have long been forced to acknowledge the existence of a large gap between the speed of the CPU and the speed of its attached I/O devices. A number of techniques have been developed in an attempt to narrow this gap, and we shall review them in this chapter key measure of magnetic disk technology is the growth in the maximum number of bits that can be stored per square inch, i. e, the bits per inch in a disk track times the number of tracks per inch of media. Called MAD, for maximal areal density, the"First Law in Disk Density " predicts [Frank, 1987 MAD=10car-1971)/10 (80.1) This is plotted against several real disk products in Fig. 80. 10. Magnetic disk technology has doubled capacity and halved price every three years, in line with the growth rate of semiconductor memory. Between 1967 and 1979 the growth in disk capacity of the average IBM data processing system more than kept up with its growth in main memory, maintaining a ratio of 1000: 1 between disk capacity and physical memory size [Stevens, 1981 In contrast to primary memory technologies, the performance of conventional magnetic disks has improved only modestly. These mechanical devices, the elements of which are described in more detail in the next section, are dominated by seek and rotation delays: from 1971 to 1981, the raw seek time for a high-end IBM disk improved by only a factor of two while the rotation time did not change[ Harker et al., 1981]. Greater recording density translates into a higher transfer rate once the information is located, and extra positioning actuators for the read/write heads can reduce the average seek time, but the raw seek time only improved at a rate of 7% per year. This is to be compared to a doubling in processor power every year, a doubling in memory density every two years, and a doubling in disk density every three years. The gap between processor performance and disk speeds continues to widen, and there is no reason to expect a radical improvement in raw disk performance in the near future To maintain balance, computer systems have been using even larger main memories or solid-state disks to buffer some of the I/O activity. This may be an acceptable solution for applications whose I/O activity has locality of reference and for which volatility is not an issue, but applications dominated by a high rate of random massive amounts of data(e.g, supercomputer applications) face a serious performance limition requests for requests for small pieces of data(e. g, transaction processing)or by a small number of sequential he rest of the chapter is organized as follows. In the next section n,we will briefly review the fundamentals of disk system architecture. The third section describes the characteristics of the applications that demand high I/O system performance. Conventional ways to improve disk performance are discussed in the last section. Basic Magnetic Disk System Architecture We will review here the basic terminology of magnetic disk devices and controllers and then examine the disk absystems of three manufacturers(IBM, Cray, and DEC). Throughout this section we are concerned with technologies that support random access, rather than sequential access(e.g, magnetic tape). A more detailed scussion, focusing on the structure of small dimension ives, can be found in Vasudeva [1988. The basic concepts are illustrated in Fig. 80. 11. A spindle consists of a collection of platters. Platters are metal disks e 2000 by CRC Press LLC
© 2000 by CRC Press LLC D. Frohmann-Bentchkowsky, “A fully decoded 2048 bit electronically programmable MOS-ROM,” Digest of Technical Papers ISSCC, vol. 14, 1971. L. A. Glasser and D. W. Dobberpuhl, The Design and Analysis of VLSI Circuits, Reading, Mass.: Addison-Wesley, 1985. F. Masuoka, “Are you ready of the next generation dynamic RAM chips,” IEEE Spectrum Magazine, vol. 27, no. 11, 1990. R. D. Pashley and S. K. Lai, “Flash memories: The best of two worlds,” IEEE Spectrum Magazine, vol. 26, no. 12, 1989. 80.2 Basic Disk System Architectures Randy H. Katz Architects of high-performance computers have long been forced to acknowledge the existence of a large gap between the speed of the CPU and the speed of its attached I/O devices. A number of techniques have been developed in an attempt to narrow this gap, and we shall review them in this chapter. A key measure of magnetic disk technology is the growth in the maximum number of bits that can be stored per square inch, i.e., the bits per inch in a disk track times the number of tracks per inch of media. Called MAD, for maximal areal density, the “First Law in Disk Density” predicts [Frank, 1987]: MAD = 10(Year-1971)/10 (80.1) This is plotted against several real disk products in Fig. 80.10. Magnetic disk technology has doubled capacity and halved price every three years, in line with the growth rate of semiconductor memory. Between 1967 and 1979 the growth in disk capacity of the average IBM data processing system more than kept up with its growth in main memory, maintaining a ratio of 1000:1 between disk capacity and physical memory size [Stevens, 1981]. In contrast to primary memory technologies, the performance of conventional magnetic disks has improved only modestly. These mechanical devices, the elements of which are described in more detail in the next section, are dominated by seek and rotation delays: from 1971 to 1981, the raw seek time for a high-end IBM disk improved by only a factor of two while the rotation time did not change [Harker et al., 1981]. Greater recording density translates into a higher transfer rate once the information is located, and extra positioning actuators for the read/write heads can reduce the average seek time, but the raw seek time only improved at a rate of 7% per year. This is to be compared to a doubling in processor power every year, a doubling in memory density every two years, and a doubling in disk density every three years. The gap between processor performance and disk speeds continues to widen, and there is no reason to expect a radical improvement in raw disk performance in the near future. To maintain balance, computer systems have been using even larger main memories or solid-state disks to buffer some of the I/O activity. This may be an acceptable solution for applications whose I/O activity has locality of reference and for which volatility is not an issue, but applications dominated by a high rate of random requests for small pieces of data (e.g., transaction processing) or by a small number of sequential requests for massive amounts of data (e.g., supercomputer applications) face a serious performance limitation. The rest of the chapter is organized as follows. In the next section, we will briefly review the fundamentals of disk system architecture. The third section describes the characteristics of the applications that demand high I/O system performance. Conventional ways to improve disk performance are discussed in the last section. Basic Magnetic Disk System Architecture We will review here the basic terminology of magnetic disk devices and controllers and then examine the disk subsystems of three manufacturers (IBM, Cray, and DEC). Throughout this section we are concerned with technologies that support random access, rather than sequential access (e.g., magnetic tape). A more detailed discussion, focusing on the structure of small dimension disk drives, can be found in Vasudeva [1988]. The basic concepts are illustrated in Fig. 80.11. A spindle consists of a collection of platters. Platters are metal disks