SiMD vectorelementlistFor example,theLD4 instruction canload oneelementinto eachoffour registers,and in this case the index is appended to the list asfollows:[V4.S - V7.S ][3] / /standard disassembly{V4.4S, V5.4S, V6.4S, V7.4S {[3] / /alternativeARMO42019-3-14
SIMD vector element list ARM04 2019-3-14 31 For example, the LD4 instruction can load one element into each of four registers, and in this case the index is appended to the list as follows: { V4.S - V7.S }[3] //standard disassembly { V4.4S, V5.4S, V6.4S, V7.4S }[3] //alternative
C1.3Addressgeneration32A64instructionset supports64-bitaddresses Valid address range is determined by factors: Size of virtual address spaceMMU configuration settings Top 8 bits of address can be used as a tagARM042019-3-14
C1.3 Address generation ARM04 2019-3-14 32 A64 instruction set supports 64-bit addresses Valid address range is determined by factors: Size of virtual address space MMU configuration settings Top 8 bits of address can be used as a tag
C1.3Address generation (cont)33 C1.3.1 Register indexed addressing C1.3.2 PC-relative addressing C1.3.3 Load/Store addressing modesARM042019-3-14
C1.3 Address generation (cont) ARM04 2019-3-14 33 C1.3.1 Register indexed addressing C1.3.2 PC-relative addressing C1.3.3 Load/Store addressing modes
C1.3.1Registerindexed addressing A64 uses base register and index register with sign-or zero-extensionand optional scalingForexampleLDR <Xt>,[<Xn/SP>,<R><m>[,<extend>[<amount>]]ARMO42019-3-14
C1.3.1 Register indexed addressing ARM04 2019-3-14 34 A64 uses base register and index register with sign- or zero-extension and optional scaling For example ◼ LDR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
C1.3.2PC-relative addressing35 A64 has support for position-independent code and data addressing:PC-relativeliteral loadshaveanoffsetrangeof +1MBProcess state flag and compare based conditional branches have a rangeof ±1MBTest bit conditional brancheshavea rangeof ±32KBUnconditional brancheshavea rangeof ±128MB PC-relative Load/Store operations,and address generation with arangeof +4GBcanbeperformedusingtwoinstructions For example: ADR <Xd>, <label>ARMO42019-3-14
C1.3.2 PC-relative addressing ARM04 2019-3-14 35 A64 has support for position-independent code and data addressing: PC-relative literal loads have an offset range of ±1MB Process state flag and compare based conditional branches have a range of ±1MB Test bit conditional branches have a range of ±32KB Unconditional branches have a range of ±128MB PC-relative Load/Store operations, and address generation with a range of ± 4GB can be performed using two instructions For example: ADR <Xd>, <label>