SiMD&FPscalarregisternames26TableC1-3siMD andfloating-point scalarregisternamesSizeName8bitsBn16bitsHn32bitsSn64bitsDn128bitsQnARM042019-3-14
SIMD & FP scalar register names ARM04 2019-3-14 26
SiMDvectorregisternames27TableC1-4SiMDvectorregisternamesNameShape8bitsx8lanesVn.8B8 bits×16 lanesVn.16B16bits×4lanesVn.4H16 bits ×8lanesVn.8H32bits×2lanesVn.25Vn.4S32bits×4 lanesVn.1D64 bits ×1 lane64bits×2lanesVn.2DLanes are the number of elements within the registerARM042019-3-14
SIMD vector register names ARM04 2019-3-14 27 Lanes are the number of elements within the register
SiMDvectorelementnames28TableC1-5VectorregisternameswithelementindexSizeName8bitsVn.B[i] =Vn.16B[i],Vn.8B[i]...16bitsVn.H[i] =Vn.8H[],Vn.4H[i]...32bitsVn.S[i] =Vn.4s[i],Vn.2S[i]..64bitsVn.D[i] =Vn.2D[],Vn.1D[]..zero-based elementARM042019-3-14
SIMD vector element names ARM04 2019-3-14 28 zero-based element =Vn.16B[i],Vn.8B[i],. =Vn.8H[i],Vn.4H[i],. =Vn.4S[i],Vn.2S[i],. =Vn.2D[i],Vn.1D[i]
SiMDvectorelementnames(cont)29 Vn.B[0] = Vn.2B[O] = Vn.4B[O] = .. Vn.B[O] ± BnVn.B[O]iselementnameandBnisscalarnameAlthough they represent the same bits in the register,they select differentinstructionencodingformsARMO42019-3-14
SIMD vector element names (cont) ARM04 2019-3-14 29 Vn.B[0] = Vn.2B[0] = Vn.4B[0] = . Vn.B[0] ≠ Bn Vn.B[0] is element name and Bn is scalar name Although they represent the same bits in the register, they select different instruction encoding forms
SIMDvectorregisterlist30 The following examples are equivalent representations of a set of fourregisters V4to V7, each holding fourlanes of 32-bit elements:{ V4.4S - V7.4S / /standard disassembly{ V4.4S, V5.4S, V6.4S, V7.4S 1 //alternativeARMO42019-3-14
SIMD vector register list ARM04 2019-3-14 30 The following examples are equivalent representations of a set of four registers V4 to V7, each holding four lanes of 32-bit elements: { V4.4S - V7.4S } //standard disassembly { V4.4S, V5.4S, V6.4S, V7.4S } //alternative