C1.3.3Load/Storeaddressingmodes36Load/Store addressing modes require a 64-bit base address fromGPRs or SP, with an optional immediate offset or index register offsetARM042019-3-14
C1.3.3 Load/Store addressing modes ARM04 2019-3-14 36 Load/Store addressing modes require a 64-bit base address from GPRs or SP, with an optional immediate offset or index register offset
Load/Storeaddressingmodes37TableC1-6A64Load/StoreaddressingmodesOffsetAddressing ModeImmediateRegisterExtendedRegisterBaseregisteronly (no[baset,#o]]offset)Baseplusoffset[baset,#imm)][base,Xmt,LSL#imm)][base,Wm,(S|U)xTw[#imm)]Pre-indexed[base,#imm]!Post-indexed[base],#imm[base], XmaLiteral (PC-relative)labela.Thepost-indexed byregister offsetmodecanbeused with theSIMDLoad/Storestructureinstructions described inLoad/StoreVectoronpageC3-139.Otherwisethepost-indexedbyregisterofifsetmodeis notavailable,ARM042019-3-14
Load/Store addressing modes ARM04 2019-3-14 37
Base registeronly(no offset38 [base]/ /mem= base / /base = baseARM042019-3-14
Base register only (no offset) ARM04 2019-3-14 38 [base] //mem = base //base = base
Base plus offset39[basel,#imm]//mem=base+imm//base=base[base, Xm/,LSL #imm]//mem=base+(XmLSL#imm)//base=base[base, Wm, (S/U)XTW {#imm)]/ /ADD Xd, base, Wm, SXTW#3 / / Xd=base+ (SignExtend(Wm) LSL3), base= base/ /ADD Xd, base, Wm, UXTH#4 // Xd =base + (ZeroExtend(Wm<15:0>) LSL4),base=baseARM042019-3-14
Base plus offset ARM04 2019-3-14 39 [base{, #imm}] //mem = base + imm //base = base [base, Xm{, LSL #imm}] //mem = base + (Xm LSL #imm) //base = base [base, Wm, (S|U)XTW {#imm}] //ADD Xd, base, Wm, SXTW #3 // Xd = base + (SignExtend(Wm) LSL 3), base = base //ADD Xd, base, Wm, UXTH #4 // Xd = base + (ZeroExtend(Wm<15:0>) LSL 4), base = base
Pre-indexed40 [base, #imm]!/ /mem= base + imm//base=base+immARM042019-3-14
Pre-indexed ARM04 2019-3-14 40 [base, #imm]! //mem = base + imm //base = base + imm