REVISED PRINTING COMPUTER ORGANIZATION AND DESIGN THE HARDWARE / SOFTWARE INTERFACE OUT REVISED 4 PRINTING DAVID A. PATTERSON JOHN L. HENNESSY MK OKAUTHAN
ARITHMETIC CORE INSTRUCTION SET ① OPCODE oya8o1 MIPS /FMT/FT Reference Data FOR- FUNGT NAME,MNEMONIC MAT OPERATION (Hex) CORE INSTRUCTION SET OPCODE Branch On FP True belt FI ifFPcondPC-PC+4+BranchAddr (4) 118/1/- FOR /FUNCT Branch On FP False beit if!FPeond)PC-PC+4+BranchAddr(4) 11/80/- NAME,MNEMONIC MAT (Hex) Divide div Lo-R[rsVR[rt]:Hi-R[rs]%R[rt] 0-1a pue g OPERATION (in Verilog) Divide Unsigned Add add R RIrd]■Rs+Rtl (1)0/20 divu R Lo-R[rsVR[rt]:Hi-R[rs]%R(rt] 60M1b FP Add Single add.s FR 11/10-0 Add Immediate add! R[rt]-R[rs]+SignExtlmm (1,2) F[fd ]F[fs]+F[ft) FPAdd add.d FR {F,Fl叶1》-F国.FE+1}+ Add Imm.Unsigned addiu Rfrt]-R[rs]+SignExtlmm (2 Double 11/11-0 F[,F+1} Add Unsigned addu R Rfrd]-Rfrs]+Rfrt] 0/21be FP Compare Single e.x.s FR FPcond -(F[fs]op F[ft])?1:0 11/10-y suunjoo)apis wonoq plod' And and R Rfrd]-Rfrs]Rfrt) 0 /24pe FP Compare Double FR eoad-+31:0 11/1-y And Immediate Rfrt]=Rfrs]ZeroExtlmm Chex is ag.it,or 1o)(op is -,or <)(y is 32.3c,or 3e) if(R(rs]--R[rt]) FP Divide Single div.s FR Fffd]-F[fs]/F[ft] 11/10/-3 Branch On Equal beg PC-PC+4+BranchAd恤 (4) FP Divide FIF+1]}-FFE+h/ 11/11/-3 ifRfrs]!-Rfnt]) Double div.d FR F[m,F[+1]} Branch On Not Equalbne PC-PC+4+BranchAddr (④ Swes FP Multiply Single mul.s FR F-F闯·F间 1/10/-2 Jump PC-JumpAddr (S) Zves FP Multiply mul.d FR F.F+I]}-Fs,F+1]}◆ 11/11/-2 Double {F[,Fi+1} Jump And Link R[31]-PC+8:PC-JumpAddr (5 3九e FP Subtract Single sub.s FR F[fd]-F[fs]-F[ft] 11/10w-1 Jump Register R PC-R[rs] 0108a FP Subtract Double sub.d FR F,F+1B-F[sF+1]}- 11/11-/1 R-{24b0,MR[s间 {F可，F+1]} Load Byte Unsigned 1bu (2) 24bex Load FP Single Iwel Ffrt]-M[RfrsH+SignExtlmm] (2)31/-/- Load Halfword Load FP F[rt]-M[R[rs]+SignExtlmm]: 1hu R[rt]-116'b0,M[R[rs] 1dc1 Unsigned +SignExtlmmM15:0)) (2) Double Ffrt+1]-M(Rfrs]+SignExtlmm+4] 2)35--- 30gex Move From Hi Load Linked 11 R Rd-H田 010 Rfrt]-M[Rfrs}+SignExtlmm] 27) Move From Lo 厘f1o R Rfrd]=Lo 0/12 Load Upper Imm 1u Rfrt]-imm,16'bo) Move From Control 里1c0 Rfrd]-CR[rs] 100W-0 Load Word R(rt]-M[R[rsH+SignExtlmm] (2) Multiply (Hi,Lo)-R(rs]*R[rt] 0.人-18 Nor nor RR[rd]-~(RIrs]|R[rt] 0 /27be Multiply Unsigned u11 Hi.Lo)R[rs]*Rfrt] (60-/19 0/25bex Shift Right Arith. R Rfrd]-R[rt]>>shamt Rfrd]-R[s]|R[rt] 0--3 or R Store FP Single M[R[rs]+SignExtlmm]-FIrt] (2)39-/- Or Immediate R(rt]-R[rs]ZeroExtlmm (3) Store FP sdel MR[rs+SignExtlmm]-FIrt]: 2)3dw-/-- Set Less Than slt R Rd-(Rs<Rt？1:0 0/2e Double M[R(rs]+SignExtlmm+4]-F[rt+1 Set Less Than Imm. sIti I Rfrt]-(Rfrs]SignExtlmm)?1 0 (2) FLOATING-POINT INSTRUCTION FORMATS Set Less Than Imm. R[rt](R[rs]SignExtlmm) FR d Buoe opeode funct Unsigned 91:0 26 0 65 Set Less Than Unsig.s1tu R Rfrd]-(R[rs]Rfrt])?1:0 (6)0/2b3 FI Imt immediate lInd'I Shift Left Logical 11 RR[rd]-Rfrt]<shamt 0100e 3到 2625 Shift Right Logical R Rfrd]-R[rt]>>shamt 0/02ea PSEUDOINSTRUCTION SET Store Byte M[R(rs}+SignExtlmm](7:0)- NAME MNEMONIC OPERATION sb R470 (2) Branch Less Than bIt ifRfrs]<Rfrt))PC-Label Store Conditional MRfrs}+SignExtlmm]-Rfrt]: Branch Greater Than bgt if(R[rs]>R[rt])PC-Label R可-(atomic)？i:0 2,7) 38bex Branch Less Than or Equal ble iRs]小-R(r])PC=Label Branch Greater Than or Equal bge if(R[rs]-R(rt])PC-Label Store Halfword M[R(rs]+SignExtlmml(15:0)= sh R15:0) (2) 29bex Load Immediate 11 RIrd-irmmedsate Move Rfrd]-R[rs] uaa5) Store Word SW I MIR(rs]+SignExtlmm]-Rfrt] (2) REGISTER NAME,NUMBER,USE.CALL CONVENTION Subtract sub RRd-R[s图-R[ (1)0/22e 0/23be NAME NUMBER USE PRESERVEDACROSS Subtract Unsigned subu R Rfrd]-R[rs]-R(rt] A CALL? pe2 (1)May cause overflow exception 5他t0 The Constant value 0 N.A. (2)SignExtlmm -{16(immediate[15]),immediate Sat Assembler Temporary No (3)ZeroExtlmm16{1b'0),immediate (4)BranchAddr(14(immediate[15]),immediate,2'b0 Svo-SvI 2-3 Values for Function Results Ne (5)JumpAddr=fP℃+431：28l.ad山es线.2"b01 and Expression Evaluation (6)Operands considered unsigned numbers (vs.2's comp.) 47 Arguments No (7)Atomic test&set pair;Rfrt]=I if pair atomic.0 if not atomic STFS17 813 Temporaries No BASIC INSTRUCTION FORMATS 5S057 16-23 Saved Temporaries 24-25 Temporaries No EL shamt Sk0-Sk1 26-27 Reserved for OS Kemel No 2120 6 5 65 28 Global Pointer Yes opcode immediate Ssp 29 Stack Pointer Yes 2625 212 615 30 上tame pointer Yes d Retumn Adress Yes Copyright 2009 by Elseviet,Inc..All rights reserved.From Patterson and Hennessy,Computer Organization and Design,4th ed
M I P S Reference Data BASIC INSTRUCTION FORMATS REGISTER NAME, NUMBER, USE, CALL CONVENTION CORE INSTRUCTION SET OPCODE NAME, MNEMONIC FORMAT OPERATION (in Verilog) / FUNCT (Hex) Add add R R[rd] = R[rs] + R[rt] (1) 0 / 20hex Add Immediate addi I R[rt] = R[rs] + SignExtImm (1,2) 8hex Add Imm. Unsigned addiu I R[rt] = R[rs] + SignExtImm (2) 9hex Add Unsigned addu R R[rd] = R[rs] + R[rt] 0 / 21hex And and R R[rd] = R[rs] & R[rt] 0 / 24hex And Immediate andi I R[rt] = R[rs] & ZeroExtImm (3) chex Branch On Equal beq I if(R[rs]==R[rt]) PC=PC+4+BranchAddr (4) 4hex Branch On Not Equal bne I if(R[rs]!=R[rt]) PC=PC+4+BranchAddr (4) 5hex Jump j J PC=JumpAddr (5) 2hex Jump And Link jal J R[31]=PC+8;PC=JumpAddr (5) 3hex Jump Register jr R PC=R[rs] 0 / 08hex Load Byte Unsigned lbu I R[rt]={24’b0,M[R[rs] +SignExtImm](7:0)} (2) 24hex Load Halfword Unsigned lhu I R[rt]={16’b0,M[R[rs] +SignExtImm](15:0)} (2) 25hex Load Linked ll I R[rt] = M[R[rs]+SignExtImm] (2,7) 30hex Load Upper Imm. lui I R[rt] = {imm, 16’b0} fhex Load Word lw I R[rt] = M[R[rs]+SignExtImm] (2) 23hex Nor nor R R[rd] = ~ (R[rs] | R[rt]) 0 / 27hex Or or R R[rd] = R[rs] | R[rt] 0 / 25hex Or Immediate ori I R[rt] = R[rs] | ZeroExtImm (3) dhex Set Less Than slt R R[rd] = (R[rs] < R[rt]) ? 1 : 0 0 / 2ahex Set Less Than Imm. slti I R[rt] = (R[rs] < SignExtImm)? 1 : 0 (2) ahex Set Less Than Imm. Unsigned sltiu I R[rt] = (R[rs] < SignExtImm) ? 1 : 0 (2,6) bhex Set Less Than Unsig. sltu R R[rd] = (R[rs] < R[rt]) ? 1 : 0 (6) 0 / 2bhex Shift Left Logical sll R R[rd] = R[rt] << shamt 0 / 00hex Shift Right Logical srl R R[rd] = R[rt] > > shamt 0 / 02hex Store Byte sb I M[R[rs]+SignExtImm](7:0) = R[rt](7:0) (2) 28hex Store Conditional sc I M[R[rs]+SignExtImm] = R[rt]; R[rt] = (atomic) ? 1 : 0 (2,7) 38hex Store Halfword sh I M[R[rs]+SignExtImm](15:0) = R[rt](15:0) (2) 29hex Store Word sw I M[R[rs]+SignExtImm] = R[rt] (2) 2bhex Subtract sub R R[rd] = R[rs] - R[rt] (1) 0 / 22hex Subtract Unsigned subu R R[rd] = R[rs] - R[rt] 0 / 23hex (1) May cause overflow exception (2) SignExtImm = { 16{immediate[15]}, immediate } (3) ZeroExtImm = { 16{1b’0}, immediate } (5) JumpAddr = { PC+4[31:28], address, 2’b0 } (7) Atomic test&set pair; R[rt] = 1 if pair atomic, 0 if not atomic R opcode rs rt rd shamt funct 31 26 25 21 20 16 15 11 10 6 5 0 I opcode rs rt immediate 31 26 25 21 20 16 15 0 J opcode address 31 26 25 0 ARITHMETIC CORE INSTRUCTION SET OPCODE NAME, MNEMONIC FORMAT OPERATION / FMT /FT / FUNCT (Hex) Branch On FP True bc1t FI if(FPcond)PC=PC+4+BranchAddr (4) 11/8/1/-- Branch On FP False bc1f FI if(!FPcond)PC=PC+4+BranchAddr(4) 11/8/0/-- Divide div R Lo=R[rs]/R[rt]; Hi=R[rs]%R[rt] 0/--/--/1a Divide Unsigned divu R Lo=R[rs]/R[rt]; Hi=R[rs]%R[rt] (6) 0/--/--/1b FP Add Single add.s FR F[fd ]= F[fs] + F[ft] 11/10/--/0 FP Add Double add.d FR {F[fd],F[fd+1]} = {F[fs],F[fs+1]} + {F[ft],F[ft+1]} 11/11/--/0 FP Compare Single c.x.s* FR FPcond = (F[fs] op F[ft]) ? 1 : 0 11/10/--/y FP Compare Double c.x.d* FR FPcond = ({F[fs],F[fs+1]} op {F[ft],F[ft+1]}) ? 1 : 0 11/11/--/y * (x is eq, lt, or le) (op is ==, <, or <=) ( y is 32, 3c, or 3e) FP Divide Single div.s FR F[fd] = F[fs] / F[ft] 11/10/--/3 FP Divide Double div.d FR {F[fd],F[fd+1]} = {F[fs],F[fs+1]} / {F[ft],F[ft+1]} 11/11/--/3 FP Multiply Single mul.s FR F[fd] = F[fs] * F[ft] 11/10/--/2 FP Multiply Double mul.d FR {F[fd],F[fd+1]} = {F[fs],F[fs+1]} * {F[ft],F[ft+1]} 11/11/--/2 FP Subtract Single sub.s FR F[fd]=F[fs] - F[ft] 11/10/--/1 FP Subtract Double sub.d FR {F[fd],F[fd+1]} = {F[fs],F[fs+1]} - {F[ft],F[ft+1]} 11/11/--/1 Load FP Single lwc1 I F[rt]=M[R[rs]+SignExtImm] (2) 31/--/--/-- Load FP Double ldc1 I F[rt]=M[R[rs]+SignExtImm]; (2) F[rt+1]=M[R[rs]+SignExtImm+4] 35/--/--/-- Move From Hi mfhi R R[rd] = Hi 0 /--/--/10 Move From Lo mflo R R[rd] = Lo 0 /--/--/12 Move From Control mfc0 R R[rd] = CR[rs] 10 /0/--/0 Multiply mult R {Hi,Lo} = R[rs] * R[rt] 0/--/--/18 Multiply Unsigned multu R {Hi,Lo} = R[rs] * R[rt] (6) 0/--/--/19 Shift Right Arith. sra R R[rd] = R[rt] >> shamt 0/--/--/3 Store FP Single swc1 I M[R[rs]+SignExtImm] = F[rt] (2) 39/--/--/-- Store FP Double sdc1 I M[R[rs]+SignExtImm] = F[rt]; (2) M[R[rs]+SignExtImm+4] = F[rt+1] 3d/--/--/-- FR opcode fmt ft fs fd funct 31 26 25 21 20 16 15 11 10 6 5 0 FI opcode fmt ft immediate 31 26 25 21 20 16 15 0 NAME MNEMONIC OPERATION Branch Less Than blt if(R[rs]<R[rt]) PC = Label Branch Greater Than bgt if(R[rs]>R[rt]) PC = Label Branch Less Than or Equal ble if(R[rs]<=R[rt]) PC = Label Branch Greater Than or Equal bge if(R[rs]>=R[rt]) PC = Label Load Immediate li R[rd] = immediate Move move R[rd] = R[rs] NAME NUMBER USE PRESERVED ACROSS A CALL? $zero 0 The Constant Value 0 N.A. $at 1 Assembler Temporary No $v0-$v1 2-3 Values for Function Results and Expression Evaluation No $a0-$a3 4-7 Arguments No $t0-$t7 8-15 Temporaries No $s0-$s7 16-23 Saved Temporaries Yes $t8-$t9 24-25 Temporaries No $k0-$k1 26-27 Reserved for OS Kernel No $gp 28 Global Pointer Yes $sp 29 Stack Pointer Yes $fp 30 Frame Pointer Yes $ra 31 Return Address Yes 1 2 MIPS Reference Data Card (“Green Card”) 1. Pull along perforation to separate card 2. Fold bottom side (columns 3 and 4) together FLOATING-POINT INSTRUCTION FORMATS PSEUDOINSTRUCTION SET Copyright 2009 by Elsevier, Inc., All rights reserved. From Patterson and Hennessy, Computer Organization and Design, 4th ed. (4) BranchAddr = { 14{immediate[15]}, immediate, 2’b0 } (6) Operands considered unsigned numbers (vs. 2 s comp.) ’ >
① IEEE 754 FLOATING-POINT ▣ OPCODES.BASE CONVERSION.ASCII SYMBOLS STANDARD IEEE 754 Symbols MIPS (1)MIPS (2)MIPS opeode Deci.Hexa.ASCII Deei.Hexa.ASCIT funct futct Binary dec.Char. dech Char 0 生0 (3126 (5:0) (50 mal mal (-1)x(1+Fraction)x 2(Exponent-Bias) 0 acter 士Denorm a11 a8d. 00000D0 0 O NUL 64 40 where Single Precision Bias-127. 0 00000D1 SOH 65 41 Double Precision Bias-1023. T to MAX-I anything F.Pt.Num. arl 000010 66 MAX 0 生o 1a1 ata 000011 3 3 上 A3 IEEE Single Precision and MAX 主0 NaN pue sllv Ud】[U 上 08 5 9 Double Precision Formats: S.P.MAX -255.D.P.MAX -2047 abs./ 000I01 ENO 000110 ACK 7 S Exponent Fraction bgt需 srav 000111 67 BEL 71 47 3130 232 0o00U B HT 7 s Exponent Fraction 74 632 a1七1 5251 OVZ a1r九rn 0010I1 b VT 75 4b MEMORY ALLOCATION STACK FRAME andi Found.w./)1100 Stack Higher 0￥1 00110 CR 77 d Argument 6 Memory 见后三1 c811.f 001110 14 78 Argument S Addresses 1u1 r1oor.w/001111 15 79 r DLE (2) 勇h 010001 I 81 aved Registers Stack novz. Dynamic Data 0I0o10 18 12 DC2 82 Grows movn./ 010011 9 Sgp+10008s000ea 1 DC3 Statie Data 10000000h ocal Variables 010101 21 15 NAK 010110 22 SYN Text 010111 pe00400000hex Lower u1七 U00 2 18 CAN 38 Memory Addresses 周B1七u 011001 )气 19 EM 59 Reserved div 011010 26 SUB 90 divu 011011 91 DATA ALIGNMENT O1100 28 FS 92 93 Double Word I 3 e 94 Word Word 011111 31 US 95 1 Halfword Halfword Halfword Halfword 1b cvt.a了 ④ addu cvt.df 10000 33 21 ByteByte Byte Byte Byte Byte Byte Byte 1w1 线o 1000I0 10011 35 9 63 Value of three least significant bits of byte address(Big Endian) cvt.w./ 00I00 0而 EXCEPTION CONTROL REGISTERS:CAUSE AND STATUS ox 100I01 101 B Interrupt Exception 10D110 诏 & 102 6 100111 103 6 D Mask Code 5101e b 31 sh 101001 41 29 105 69 Pending U EI sIt 101010 106 6 sItu 101011 Interrupt 3 M LE I= 108 BD-Branch Delay,UM-User Mode.EL-Exception Level,IE -Interrupt Enable 101101 45 109 6d EXCEPTION CODES WE 101110 46 2e 110 111 f Number Name Number Name 101111 Cause of Exception Cause of Exception 11 ctr 1000 48 30 0 112 70 0 Int Bp Breakpoint Exception c.un/ 9 31 113 Aderess frror exception AdEL 10 RI Reserved Instruction c.g./ 110010 14 (load or instruction fetch) Exception pror tItu c.ueg 110011 51 115 73 5 AdEs Address上rot上Excep0n 116 11 CpU Coprocessor c.olt. (store) mplemented 41 c.ult. 110101 53 5 17 15 IBE Bus Error on 12 Ov 1g2 tne 0.010 110110 6 118 6 6 Instruction Fetch Exception c.ulaf 110111 车写 119 7 c.st 36 DBE Bus Error on 13 Tr Load or Store Trap swcl 111001 9 121 8 58 Sys Syscall Exception 15 FPE Floating Point Exception 111010 3a 122 7a c.ngi/ 111011 123 SIZE PREFIXES (10%for Disk,Communication:2*for Memory) 125 7d PRE. PRE. PRE. PRE. 111101 61 SIE 7 c.1/ 111110 62 3 126 FIX FIX SIZE FIX FIX c.ng 111111 6 27 DEL 103,20Klo 105,20Peta- 10 milli- femto- (1)opcode(31F26)=0 10,220Mega 101,2Exa 106 micro- 10客 (2)opcode(31:26)--17n (1lhex):if fmt(25:21) 16in (10pex)s (single): 10.20Gga 1021,270 Zetta. 109a0- 1027 if fmnt(25:21)-17n()f-d (double) 102 240 Tera- 10,20Yota 0 yocto- The symbol for each prefix is just its first letter,except u is used for micro. Copyright 2009 by Elsevier,Ine.,All rights reserved.From Patterson and Hennessy.Computer Organization and Design,4th ed. SaIW
... Argument 6 Argument 5 Saved Registers Local Variables OPCODES, BASE CONVERSION, ASCII SYMBOLS (1) opcode(31:26) == 0 (2) opcode(31:26) == 17ten (11hex); if fmt(25:21)==16ten (10hex) f = s (single); if fmt(25:21)==17ten (11hex) f = d (double) STANDARD (-1)S × (1 + Fraction) × 2(Exponent - Bias) where Single Precision Bias = 127, Double Precision Bias = 1023. IEEE Single Precision and Double Precision Formats: MEMORY ALLOCATION $sp 7fff fffchex $gp 1000 8000hex 1000 0000hex pc 0040 0000hex 0hex DATA ALIGNMENT EXCEPTION CONTROL REGISTERS: CAUSE AND STATUS EXCEPTION CODES SIZE PREFIXES (10x for Disk, Communication; 2x for Memory) The symbol for each prefix is just its first letter, except μ is used for micro. MIPS opcode (31:26) (1) MIPS funct (5:0) (2) MIPS funct (5:0) Binary Decimal Hexadecimal ASCII Character Decimal Hexadecimal ASCII Character (1) sll add.f 00 0000 0 0 NUL 64 40 @ sub.f 00 0001 1 1 SOH 65 41 A j srl mul.f 00 0010 2 2 STX 66 42 B jal sra div.f 00 0011 3 3 ETX 67 43 C beq sllv sqrt.f 00 0100 4 4 EOT 68 44 D bne abs.f 00 0101 5 5 ENQ 69 45 E blez srlv mov.f 00 0110 6 6 ACK 70 46 F bgtz srav neg.f 00 0111 7 7 BEL 71 47 G addi jr 00 1000 8 8 BS 72 48 H addiu jalr 00 1001 9 9 HT 73 49 I slti movz 00 1010 10 a LF 74 4a J sltiu movn 00 1011 11 b VT 75 4b K andi syscall round.w.f 00 1100 12 c FF 76 4c L ori break trunc.w.f 00 1101 13 d CR 77 4d M xori ceil.w.f 00 1110 14 e SO 78 4e N lui sync floor.w.f 00 1111 15 f SI 79 4f O mfhi 01 0000 16 10 DLE 80 50 P (2) mthi 01 0001 17 11 DC1 81 51 Q mflo movz.f 01 0010 18 12 DC2 82 52 R mtlo movn.f 01 0011 19 13 DC3 83 53 S 01 0100 20 14 DC4 84 54 T 01 0101 21 15 NAK 85 55 U 01 0110 22 16 SYN 86 56 V 01 0111 23 17 ETB 87 57 W mult 01 1000 24 18 CAN 88 58 X multu 01 1001 25 19 EM 89 59 Y div 01 1010 26 1a SUB 90 5a Z divu 01 1011 27 1b ESC 91 5b [ 01 1100 28 1c FS 92 5c \ 01 1101 29 1d GS 93 5d ] 01 1110 30 1e RS 94 5e ^ 01 1111 31 1f US 95 5f _ lb add cvt.s.f 10 0000 32 20 Space 96 60 ‘ lh addu cvt.d.f 10 0001 33 21 ! 97 61 a lwl sub 10 0010 34 22 " 98 62 b lw subu 10 0011 35 23 # 99 63 c lbu and cvt.w.f 10 0100 36 24 $ 100 64 d lhu or 10 0101 37 25 % 101 65 e lwr xor 10 0110 38 26 & 102 66 f nor 10 0111 39 27 ’ 103 67 g sb 10 1000 40 28 ( 104 68 h sh 10 1001 41 29 ) 105 69 i swl slt 10 1010 42 2a * 106 6a j sw sltu 10 1011 43 2b + 107 6b k 10 1100 44 2c , 108 6c l 10 1101 45 2d - 109 6d m swr 10 1110 46 2e . 110 6e n cache 10 1111 47 2f / 111 6f o ll tge c.f.f 11 0000 48 30 0 112 70 p lwc1 tgeu c.un.f 11 0001 49 31 1 113 71 q lwc2 tlt c.eq.f 11 0010 50 32 2 114 72 r pref tltu c.ueq.f 11 0011 51 33 3 115 73 s teq c.olt.f 11 0100 52 34 4 116 74 t ldc1 c.ult.f 11 0101 53 35 5 117 75 u ldc2 tne c.ole.f 11 0110 54 36 6 118 76 v c.ule.f 11 0111 55 37 7 119 77 w sc c.sf.f 11 1000 56 38 8 120 78 x swc1 c.ngle.f 11 1001 57 39 9 121 79 y swc2 c.seq.f 11 1010 58 3a : 122 7a z c.ngl.f 11 1011 59 3b ; 123 7b { c.lt.f 11 1100 60 3c < 124 7c | sdc1 c.nge.f 11 1101 61 3d = 125 7d } sdc2 c.le.f 11 1110 62 3e > 126 7e ~ c.ngt.f 11 1111 63 3f ? 127 7f DEL S Exponent Fraction 31 30 23 22 0 S Exponent Fraction 63 62 52 51 0 Double Word Word Word Byte Byte Byte Byte Byte Byte Byte Byte 0 1 2 3 4 5 6 7 Value of three least significant bits of byte address (Big Endian) B D Interrupt Mask Exception Code 31 15 8 6 2 Pending Interrupt U M E L I E 15 8 4 1 0 Number Name Cause of Exception Number Name Cause of Exception 0 Int Interrupt (hardware) 9 Bp Breakpoint Exception 4 AdEL Address Error Exception (load or instruction fetch) 10 RI Reserved Instruction Exception 5 AdES Address Error Exception (store) 11 CpU Coprocessor Unimplemented 6 IBE Bus Error on Instruction Fetch 12 Ov Arithmetic Overflow Exception 7 DBE Bus Error on Load or Store 13 Tr Trap 8 Sys Syscall Exception 15 FPE Floating Point Exception SIZE PREFIX SIZE PREFIX SIZE PREFIX SIZE PREFIX 103, 210 Kilo- 1015, 250 Peta- 10-3 milli- 10-15 femto- 106, 220 Mega- 1018, 260 Exa- 10-6 micro- 10-18 atto- 109, 230 Giga- 1021, 270 Zetta- 10-9 nano- 10-21 zepto- 1012, 240 Tera- 1024, 280 Yotta- 10-12 pico- 10-24 yocto- 3 Stack Dynamic Data Static Data Text Reserved IEEE 754 Symbols S.P. MAX = 255, D.P. MAX = 2047 Exponent Fraction Object 0 0 ± 0 0 ≠0 ± Denorm 1 to MAX - 1 anything ± Fl. Pt. Num. MAX 0 ±∞ MAX ≠0 NaN STACK FRAME Higher Memory Addresses Lower Memory Addresses Stack Grows $sp $fp 4 MIPS Reference Data Card (“Green Card”) 1. Pull along perforation to separate card 2. Fold bottom side (columns 3 and 4) together IEEE 754 FLOATING-POINT Halfword Halfword Halfword Halfword BD = Branch Delay, UM = User Mode, EL = Exception Level, IE =Interrupt Enable Copyright 2009 by Elsevier, Inc., All rights reserved. From Patterson and Hennessy, Computer Organization and Design, 4th ed
In Praise of Computer Organization and Design:The Hardware/ Software Interface,Revised Fourth Edition "Patterson and Hennessy not only improve the pedagogy of the traditional mate- rial on pipelined processors and memory hierarchies,but also greatly expand the multiprocessor coverage to include emerging multicore processors and GPUs.The fourth edition of Computer Organization and Design sets a new benchmark against which all other architecture books must be compared." -David A.Wood,University of Wisconsin-Madison "Patterson and Hennessy have greatly improved what was already the gold stan- dard of textbooks.In the rapidly evolving field of computer architecture,they have woven an impressive number of recent case studies and contemporary issues into a framework of time-tested fundamentals." -Fred Chong,University of California at Santa Barbara "Since the publication of the first edition in 1994,Computer Organization and Design has introduced a generation of computer science and engineering students to computer architecture.Now,many of those students have become leaders in the field.In academia,the tradition continues as faculty use the latest edition of the book that inspired them to engage the next generation.With the fourth edition, readers are prepared for the next era of computing." -David I.August,Princeton University "The new coverage of multiprocessors and parallelism lives up to the standards of this well-written classic.It provides well-motivated,gentle introductions to the new topics,as well as many details and examples drawn from current hardware." -John Greiner,Rice University "As computer hardware architecture moves from uniprocessor to multicores,the parallel programming environments used to take advantage of these cores will be a defining challenge to the success of these new systems.In the multicore systems, the interface between the hardware and software is of particular importance.This new edition of Computer Organization and Design is mandatory for any student who wishes to understand multicore architecture including the interface between programming it and its architecture." -Jesse Fang,Director of Programming System Lab at Intel "The fourth edition of Computer Organization and Design continues to improve the high standards set by the previous editions.The new content,on trends that are reshaping computer systems including multicores,Flash memory,GPUs,etc., makes this edition a must read-even for all of those who grew up on previous editions of the book” -Parthasarathy Ranganathan,Principal Research Scientist,HP Labs
In Praise of Computer Organization and Design: The Hardware/ Software Interface, Revised Fourth Edition “Patterson and Hennessy not only improve the pedagogy of the traditional material on pipelined processors and memory hierarchies, but also greatly expand the multiprocessor coverage to include emerging multicore processors and GPUs. The fourth edition of Computer Organization and Design sets a new benchmark against which all other architecture books must be compared.” —David A. Wood, University of Wisconsin-Madison “Patterson and Hennessy have greatly improved what was already the gold standard of textbooks. In the rapidly evolving field of computer architecture, they have woven an impressive number of recent case studies and contemporary issues into a framework of time-tested fundamentals.” —Fred Chong, University of California at Santa Barbara “Since the publication of the first edition in 1994, Computer Organization and Design has introduced a generation of computer science and engineering students to computer architecture. Now, many of those students have become leaders in the field. In academia, the tradition continues as faculty use the latest edition of the book that inspired them to engage the next generation. With the fourth edition, readers are prepared for the next era of computing.” —David I. August, Princeton University “The new coverage of multiprocessors and parallelism lives up to the standards of this well-written classic. It provides well-motivated, gentle introductions to the new topics, as well as many details and examples drawn from current hardware.” —John Greiner, Rice University “As computer hardware architecture moves from uniprocessor to multicores, the parallel programming environments used to take advantage of these cores will be a defining challenge to the success of these new systems. In the multicore systems, the interface between the hardware and software is of particular importance. This new edition of Computer Organization and Design is mandatory for any student who wishes to understand multicore architecture including the interface between programming it and its architecture.” —Jesse Fang, Director of Programming System Lab at Intel “The fourth edition of Computer Organization and Design continues to improve the high standards set by the previous editions. The new content, on trends that are reshaping computer systems including multicores, Flash memory, GPUs, etc., makes this edition a must read—even for all of those who grew up on previous editions of the book.” —Parthasarathy Ranganathan, Principal Research Scientist, HP Labs
ACKNOWLEDG MENTS Figures 1.7,1.8 Courtesy of Other World Computing (www.macsales.com).Figure 1.10.6 Courtesy of the Computer History Museum. Figures 1.9,1.19,5.37 Courtesy of AMD. Figures 5.12.1,5.12.2 Courtesy of Museum of Science,Boston. Figure 1.10 Courtesy of Storage Technology Corp. Figure 5.12.4 Courtesy of MIPS Technologies,Inc. Figures 1.10.1,1.10.2,4.15.2 Courtesy of the Charles Babbage Figures 6.15,6.16,6.17 Courtesy of Sun Microsystems,Inc. Institute,University of Minnesota Libraries,Minneapolis. Figure 6.4 Peg Skorpinski. Figures1.10.3,4.15.l,4.15.3,5.12.3,6.14.2 Courtesy of IBM. Figure 6.14.1 Courtesy of the Computer Museum of America. Figure 1.10.4 Courtesy of Cray Inc. Figure 6.14.3 Courtesy of the Commercial Computing Museum. Figure 1.10.5 Courtesy of Apple Computer,Inc. Figures 7.13.1 Courtesy of NASA Ames Research Center
A C K N O W L E D G M E N T S Figures 1.7, 1.8 Courtesy of Other World Computing (www.macsales.com). Figures 1.9, 1.19, 5.37 Courtesy of AMD. Figure 1.10 Courtesy of Storage Technology Corp. Figures 1.10.1, 1.10.2, 4.15.2 Courtesy of the Charles Babbage Institute, University of Minnesota Libraries, Minneapolis. Figures 1.10.3, 4.15.1, 4.15.3, 5.12.3, 6.14.2 Courtesy of IBM. Figure 1.10.4 Courtesy of Cray Inc. Figure 1.10.5 Courtesy of Apple Computer, Inc. Figure 1.10.6 Courtesy of the Computer History Museum. Figures 5.12.1, 5.12.2 Courtesy of Museum of Science, Boston. Figure 5.12.4 Courtesy of MIPS Technologies, Inc. Figures 6.15, 6.16, 6.17 Courtesy of Sun Microsystems, Inc. Figure 6.4 © Peg Skorpinski. Figure 6.14.1 Courtesy of the Computer Museum of America. Figure 6.14.3 Courtesy of the Commercial Computing Museum. Figures 7.13.1 Courtesy of NASA Ames Research Center