Serra, M., Dervisoglu, B.I. Testing The electrical Engineering Handbook Ed. Richard C. Dorf Boca Raton CRC Press llc. 2000
Serra, M., Dervisoglu, B.I. “Testing” The Electrical Engineering Handbook Ed. Richard C. Dorf Boca Raton: CRC Press LLC, 2000
85 esting 85.1 Digital IC Testing Micaela serra Taxonomy of Testing. Fault Models. Test Pattern Generation Output Response Analysis Bulent I. Dervisoglu 85.2 Design for Test The Testability Problem. Design for Testability. Future for Design Hewlett-Packard Company for Test 85.1 Digital IC Testing Micaela serra In this section we give an overview of digital testing techniques with appropriate reference to material containing all details of the methodology and algorithms. First, we present a general introduction of terminology and a taxonomy of testing methods. Next, we present a definition of fault models, and finally we discuss the main approaches for test pattern generation and data compaction, respectively Taxonomy of Testing The evaluation of the reliability and quality of a digital IC is commonly called testing, yet it comprises distinct phases that are mostly kept separate both in the research community and in industrial practice 1. Verification is the initial phase in which the first prototype chips are"tested"to ensure that they match their functional specification, that is, to verify the correctness of the design Verification checks that all design rules are adhered to, from layout to electrical parameters; more generally, this type of functional testing checks that the circuit: (a)implements what it is supposed to do and(b)does not do what it is not supposed to do Both conditions are necessary. This type of evaluation is done at the design sta and uses a variety of techniques, induding logic verification with the use of hardware description languages, full functional simulation, and generation of functional test vectors. We do not discuss verification techniques here 2. Testing correctly refers to the phase when one must ensure that only defect-free production chips are ackaged and shipped and detect faults arising from manufacturing and/or wear-out. Testing methods must(a)be fast enough to be applied to large amounts of chips during production,(b) take into consideration whether the industry concerned has access to large expensive external tester machines, and(c)consider whether the implementation of built-in self-test(BIST) proves to be advantageous In BIST, the circuit is designed to include its own self-testing extra circuitry and thus can signal directly, luring testing, its possible failure status. Of course, this involves a certain amount of overhead in area, and trade-offs must be considered. The development of appropriate testing algorithms and their tool support can require a large amount of engineering effort, but one must note that it may need to be done only once per design. The speed of application of the algorithm(applied to many copies of the chips c 2000 by CRC Press LLC
© 2000 by CRC Press LLC 85 Testing 85.1 Digital IC Testing Taxonomy of Testing • Fault Models • Test Pattern Generation • Output Response Analysis 85.2 Design for Test The Testability Problem • Design for Testability • Future for Design for Test 85.1 Digital IC Testing Micaela Serra In this section we give an overview of digital testing techniques with appropriate reference to material containing all details of the methodology and algorithms. First, we present a general introduction of terminology and a taxonomy of testing methods. Next, we present a definition of fault models, and finally we discuss the main approaches for test pattern generation and data compaction, respectively. Taxonomy of Testing The evaluation of the reliability and quality of a digital IC is commonly called testing, yet it comprises distinct phases that are mostly kept separate both in the research community and in industrial practice. 1. Verification is the initial phase in which the first prototype chips are “tested” to ensure that they match their functional specification, that is, to verify the correctness of the design. Verification checks that all design rules are adhered to, from layout to electrical parameters; more generally, this type of functional testing checks that the circuit: (a) implements what it is supposed to do and (b) does not do what it is not supposed to do. Both conditions are necessary. This type of evaluation is done at the design stage and uses a variety of techniques, including logic verification with the use of hardware description languages, full functional simulation, and generation of functional test vectors. We do not discuss verification techniques here. 2. Testing correctly refers to the phase when one must ensure that only defect-free production chips are packaged and shipped and detect faults arising from manufacturing and/or wear-out. Testing methods must (a) be fast enough to be applied to large amounts of chips during production, (b) take into consideration whether the industry concerned has access to large expensive external tester machines, and (c) consider whether the implementation of built-in self-test (BIST) proves to be advantageous. In BIST, the circuit is designed to include its own self-testing extra circuitry and thus can signal directly, during testing, its possible failure status. Of course, this involves a certain amount of overhead in area, and trade-offs must be considered. The development of appropriate testing algorithms and their tool support can require a large amount of engineering effort, but one must note that it may need to be done only once per design. The speed of application of the algorithm (applied to many copies of the chips) can be of more importance. Micaela Serra University of Victoria Bulent I. Dervisoglu Hewlett-Packard Company
3. Parametric testing is done to ensure that components meet design specification for delays, voltages, power, etc. Lately much attention has been given to IpDg testing, a parametric technique for CMOS testing IDDa testing monitors the current Iop that a draws when it is in a quiescent state. It is used to detect faults such as bridging faults, transistor stuck-open faults, or gate oxide leaks, which increase the normal low Ipp Jacomino et al., 1989] The density of circuitry continues to increase, while the number of I/o pins remains small. This causes a serious escalation of complexity, and testing is becoming one of the major costs to industry(estimated up to 0%) ICs should be tested before and after packaging, after mounting on a board, and periodically during operation. Different methods may be necessary for each case. Thus by testing we imply the means by which some qualities or attributes are determined to be fault-free or faulty. The main purpose of testing is the detection of malfunctions( Go/NoGo test), and only subsequently one may be interested in the actual location of the malfunction; this is called fault diagnosis or fault location. Most testing techniques are designed to be applied to combinational circuits only. While this may appear a strong restriction, in practice it is a realistic assumption based on the idea of designing a sequential circuit by partitioning the memory elements from the control functionality such that the circuit can be reconfigured ombinational at testing time. This general approach is one of the methods in design for testability(DFT)(see Section 85.2). DFT encompasses any design strategy aimed at enhancing the testability of a circuit. In particular, an design is the best-known implementation for separating the latches from the combinational gates such that some of the latches can also be reconfigured and used as either tester units or as input generator units (essential for built-in testing). Figure 85. 1(a)shows the general division for algorithms in testing. Test pattern generation implies a fair amount of work in generating an appropriate subset of all input combinations, such that a desired percentage of faults is activated and observed at the outputs. Output response analysis encompasses methods which capture only the output stream, with appropriate transformations, with the assumption that the circuit is stimulated by either an exhaustive or a random set of input combinations. Both methodologies are introduced below. Moreover a further division can be seen between on-line and off-line methods [see Fig. 85.1(b)]. In the former, each output word from the circuit is tested during normal operation. In the latter, the circuit must suspend ormal operation and enter a"test mode, at which time the appropriate method of testing is applied. while off-line testing can be executed either through external testing(a tester machine external to the circuitry)or through the use of BIST, on-line testing(also called concurrent checking)usually implies that the circuit contains ome coding scheme which has been previously embedded in the design of the circuitry If many defects are present during the manufacturing process, the manufacturing yield is lowered, and testing becomes of paramount importance. Some estimation can be given about the relationship between manufac turing yield, effectiveness of testing and defect level remaining after test [Williams, 1986). Let Y denote the yield, where Y is some value between 1(100% defect-free production) and 0(all circuits faulty after testing) Testing metho Testing Methods enter test mode during normal generation ATPG .concurrent checking BIST) or (BIT) pseudo-random FIGURE 85.1 Taxonomy of testing methods. (a) Test pattern generation;(b)on-line and off-line methods e 2000 by CRC Press LLC
© 2000 by CRC Press LLC 3. Parametric testing is done to ensure that components meet design specification for delays, voltages, power, etc. Lately much attention has been given to IDDq testing, a parametric technique for CMOS testing. IDDq testing monitors the current IDD that a circuit draws when it is in a quiescent state. It is used to detect faults such as bridging faults, transistor stuck-open faults, or gate oxide leaks, which increase the normally low IDD [Jacomino et al., 1989]. The density of circuitry continues to increase, while the number of I/O pins remains small. This causes a serious escalation of complexity, and testing is becoming one of the major costs to industry (estimated up to 30%). ICs should be tested before and after packaging, after mounting on a board, and periodically during operation. Different methods may be necessary for each case. Thus by testing we imply the means by which some qualities or attributes are determined to be fault-free or faulty. The main purpose of testing is the detection of malfunctions (Go/NoGo test), and only subsequently one may be interested in the actual location of the malfunction; this is called fault diagnosis or fault location. Most testing techniques are designed to be applied to combinational circuits only. While this may appear a strong restriction, in practice it is a realistic assumption based on the idea of designing a sequential circuit by partitioning the memory elements from the control functionality such that the circuit can be reconfigured as combinational at testing time. This general approach is one of the methods in design for testability (DFT) (see Section 85.2). DFT encompasses any design strategy aimed at enhancing the testability of a circuit. In particular, scan design is the best-known implementation for separating the latches from the combinational gates such that some of the latches can also be reconfigured and used as either tester units or as input generator units (essential for built-in testing). Figure 85.1(a) shows the general division for algorithms in testing. Test pattern generation implies a fair amount of work in generating an appropriate subset of all input combinations, such that a desired percentage of faults is activated and observed at the outputs. Output response analysis encompasses methods which capture only the output stream, with appropriate transformations, with the assumption that the circuit is stimulated by either an exhaustive or a random set of input combinations. Both methodologies are introduced below. Moreover a further division can be seen between on-line and off-line methods [see Fig. 85.1(b)]. In the former, each output word from the circuit is tested during normal operation. In the latter, the circuit must suspend normal operation and enter a “test mode,” at which time the appropriate method of testing is applied. While off-line testing can be executed either through external testing (a tester machine external to the circuitry) or through the use of BIST, on-line testing (also called concurrent checking) usually implies that the circuit contains some coding scheme which has been previously embedded in the design of the circuitry. If many defects are present during the manufacturing process, the manufacturing yield is lowered, and testing becomes of paramount importance. Some estimation can be given about the relationship between manufacturing yield, effectiveness of testing and defect level remaining after test [Williams, 1986]. Let Y denote the yield, where Y is some value between 1 (100% defect-free production) and 0 (all circuits faulty after testing). FIGURE 85.1 Taxonomy of testing methods. (a) Test pattern generation; (b) on-line and off-line methods
Let FC be the fault coverage, calculated as the percentage of detected faults over the total number of detectable modeled faults(see below for fault models). The value of FC ranges from 1(all possible faults detected)to 0 o testing done). We are interested in the final defect level (DL), after test, defined as the probability of shipping a defective product. It has been shown that tests with high fault coverage(for certain fault models, see below also have high defect coverage. The empirical equation is DL=(1-Yl-FC)100% Plotting this equation gives interesting and practical results. Table 85.1 shows only a TABLE 85. 1 Examples few examples of some practical values of Y and FC. The main conclusion to be drawn of Defect Levels is that a very high fault coverage must be achieved to obtain any acceptable defect y level value, and manufacturing yield must be continually improved to maintain reli- 0.15 ability of shipped products Fault models At the defect level, an enormous number of different failures could be present, and it is totally infeasible to alyze them as such. Thus failures are grouped together with regards to their logical fault effect on the functionality of the circuit, and this leads to the construction of logical fault models as the basis for testing algorithms [Abramovici et al., 1992]. More precisely, a fault denotes the physical failure mechanism, the fault effect denotes the logical effect of a fault on a signal-carrying net, and an error is defined as the condition(or state)of a system containing a fault( deviation from correct state). Faults can be further divided into classes, as shown in Fig. 85. 2. Here we discuss only permanent faults, that is, faults in existence long enough to be observed at test time, as opposed to temporary faults(transient or intermittent), which appear and disappear in short intervals of time, or delay faults, which affect the operating speed of the circuit. Moreover we do not discuss sequential faults, which cause a combinational circuit to behave like a sequential one, as they are mainly restricted to certain technologies (e.g, CMOS) The most commonly used fault model is that of a stuck-at fault, which is modeled by having a line segment Ick at logic 0 or 1 (stuck-at 1 or stuck-at 0). One may consider single or multiple stuck-at faults and Fig 85.3 shows an example for a simple circuit. The fault-free function is shown as F while the faulty functions, under Testing physical duration transient Intermittent FIGURE 85.2 Fault characteristics x1 F=x1 x2 +x2 x3 5 1/0:F°=X2x3 FIGURE 85.3 Single stuck-at fault example e 2000 by CRC Press LLC
© 2000 by CRC Press LLC Let FC be the fault coverage, calculated as the percentage of detected faults over the total number of detectable modeled faults (see below for fault models). The value of FC ranges from 1 (all possible faults detected) to 0 (no testing done).We are interested in the final defect level (DL), after test, defined as the probability of shipping a defective product. It has been shown that tests with high fault coverage (for certain fault models, see below) also have high defect coverage. The empirical equation is DL = (1 – Y 1-F C ) 100% Plotting this equation gives interesting and practical results. Table 85.1 shows only a few examples of some practical values of Y and FC. The main conclusion to be drawn is that a very high fault coverage must be achieved to obtain any acceptable defect level value, and manufacturing yield must be continually improved to maintain reliability of shipped products. Fault Models At the defect level, an enormous number of different failures could be present, and it is totally infeasible to analyze them as such. Thus failures are grouped together with regards to their logical fault effect on the functionality of the circuit, and this leads to the construction of logical fault models as the basis for testing algorithms [Abramovici et al., 1992]. More precisely, a fault denotes the physical failure mechanism, the fault effect denotes the logical effect of a fault on a signal-carrying net, and an error is defined as the condition (or state) of a system containing a fault (deviation from correct state). Faults can be further divided into classes, as shown in Fig. 85.2. Here we discuss only permanent faults, that is, faults in existence long enough to be observed at test time, as opposed to temporary faults (transient or intermittent), which appear and disappear in short intervals of time, or delay faults, which affect the operating speed of the circuit. Moreover we do not discuss sequential faults, which cause a combinational circuit to behave like a sequential one, as they are mainly restricted to certain technologies (e.g., CMOS). The most commonly used fault model is that of a stuck-at fault, which is modeled by having a line segment stuck at logic 0 or 1 (stuck-at 1 or stuck-at 0). One may consider single or multiple stuck-at faults and Fig. 85.3 shows an example for a simple circuit. The fault-free function is shown as F, while the faulty functions, under FIGURE 85.2 Fault characteristics. FIGURE 85.3 Single stuck-at fault example. TABLE 85.1 Examples of Defect Levels Y FC DL 0.15 0.90 0.18 0.25 0.00 0.75 0.25 0.90 0.15
0 1c1 c 10l|1110)00{1 [esIs e> Minimal Test Set T: I(01),(10).(11)I FIGURE 85.4 Test set example the occurrence of the single stuck-at faults of either line 1 stuck-at 0(1/0)or of line 2 stuck-at 1(2/1),are Bridging faults occur when two or more lines are shorted together. There are two main nalysis of bridging faults: (1)the theoretical number of possible such faults is extremely operational effect is of a wired logic AND or OR, depending on technology, and it can ever effects in complex CMOS gates CMOS stuck-open faults have been examined recently, as they cannot be modeled from the more classical fault models and are restricted to the CMOS technology. They occur when the path through one of the p-channel or one of the n-channel transistors becomes an open circuit. The main difficulty in detecting this type of fault is that it changes the combinational behavior of a cell into a sequential one. Thus the logical effect is to retain, on a given line, the previous value, introducing a memory state. To detect such a fault, one must apply two stimuli: the first to set a line at a certain value and the second to try and change that value. This, of course, ncreases the complexity of fault detection. Test Pattern generation Test pattern generation is the process of generating a(minimal) set of input patterns to stimulate the inputs of a circuit such that detectable faults can be exercised (if present)[Abramovici et al., 1992]. The process can be divided in two distinct phases: (1)derivation of a test and(2)application of a test. For(1), one must first select appropriate models for the circuit(gate or transistor level)and for faults; one must construct the test such that the output signal from a faulty circuit is different from that of a good circuit. This can be computa- tionally very expensive, but one must remember that the process is done only once at the end of the design age. The generation of a test set can be obtained either by manual methods, by algorithmic methods(with or without heuristics), or by pseudo-random methods On the other hand, for(2), a test is subsequently applied many times to each IC and thus must be efficient both in space(storage requirements for the patterns)and time. Often such a set is not minimal, as near minimality may be sufficient. The main considerations in evaluating a test set are the time to construct a minimal test set; the size of the test pattern generator, le,the load the test patterns; and the equipment required (if external)or the BISt overhead. Most algorithmic test pattern generators are based on the concept of sensitized paths. Given a line in a circuit, one wants to find a sensitized path to take a possible error all the way to an observable output. For example, to sensitize a path that goes through one input of an AND gate, one must set all other inputs of the gate to logic I to permit the sensitized signal to carry through. Figure 85. 4 summarizes the underlying principles of trying to construct a test set. Each column shows the expected output for each input combination of a NAnD gate. Columns 3 to 8 show the output under the presence of a stuck-at fault as per label. The output bits that permit detection of the corresponding fault are shown in a square, and thus at the bottom the minimal test set is listed, comprising the minimal number of distinct patterns necessary to detect all single stuck-at faults e 2000 by CRC Press LLC
© 2000 by CRC Press LLC the occurrence of the single stuck-at faults of either line 1 stuck-at 0 (1/0) or of line 2 stuck-at 1 (2/1), are shown as F*. Bridging faults occur when two or more lines are shorted together. There are two main problems in the analysis of bridging faults: (1) the theoretical number of possible such faults is extremely high and (2) the operational effect is of a wired logic AND or OR, depending on technology, and it can even have different effects in complex CMOS gates. CMOS stuck-open faults have been examined recently, as they cannot be modeled from the more classical fault models and are restricted to the CMOS technology. They occur when the path through one of the p-channel or one of the n-channel transistors becomes an open circuit. The main difficulty in detecting this type of fault is that it changes the combinational behavior of a cell into a sequential one. Thus the logical effect is to retain, on a given line, the previous value, introducing a memory state. To detect such a fault, one must apply two stimuli: the first to set a line at a certain value and the second to try and change that value. This, of course, increases the complexity of fault detection. Test Pattern Generation Test pattern generation is the process of generating a (minimal) set of input patterns to stimulate the inputs of a circuit such that detectable faults can be exercised (if present) [Abramovici et al., 1992]. The process can be divided in two distinct phases: (1) derivation of a test and (2) application of a test. For (1), one must first select appropriate models for the circuit (gate or transistor level) and for faults; one must construct the test such that the output signal from a faulty circuit is different from that of a good circuit. This can be computationally very expensive, but one must remember that the process is done only once at the end of the design stage. The generation of a test set can be obtained either by manual methods, by algorithmic methods (with or without heuristics), or by pseudo-random methods. On the other hand, for (2), a test is subsequently applied many times to each IC and thus must be efficient both in space (storage requirements for the patterns) and in time. Often such a set is not minimal, as near minimality may be sufficient. The main considerations in evaluating a test set are the time to construct a minimal test set; the size of the test pattern generator, i.e., the software or hardware module used to stimulate the circuit under test; the size of the test set itself; the time to load the test patterns; and the equipment required (if external) or the BIST overhead. Most algorithmic test pattern generators are based on the concept of sensitized paths. Given a line in a circuit, one wants to find a sensitized path to take a possible error all the way to an observable output. For example, to sensitize a path that goes through one input of an AND gate, one must set all other inputs of the gate to logic 1 to permit the sensitized signal to carry through. Figure 85.4 summarizes the underlying principles of trying to construct a test set. Each column shows the expected output for each input combination of a NAND gate. Columns 3 to 8 show the output under the presence of a stuck-at fault as per label. The output bits that permit detection of the corresponding fault are shown in a square, and thus at the bottom the minimal test set is listed, comprising the minimal number of distinct patterns necessary to detect all single stuck-at faults. FIGURE 85.4 Test set example