R type Instruction Data stream 0000 0001 0010 ALU operation 与或加喊 ALU控制线功 control 0110 0111 小于则置位 ALEC 1100 或非 Rewrite b rs Read reg.addressE 6 Read datal b rt Read reg. address2 ero Registers rd write reg. address ABU resu Read data2 Write data 32bits data
R type Instruction & Data stream op(6) rs(5) rt(5) rd(5) shamt func(6) rs rt rd Registers Read reg. address1 Read reg. address2 Write reg. address Write data Read data1 Read data2 ALU result ALU Zero 4 RegWrite ALU operation control 32bits data ALUC ALU 控制线 功能 0000 与 0001 或 0010 加 0110 减 0111 小于则置位 1100 或非
I type Instruction Data stream lw$to,200($s2) ALOt control H sw$to,200($s2) Rewrite ALEC ALU operation Read reg. addre 6 2 Read data1 rt Read reg. ac Zerol Men write Registers rt Write reg. address U resul ddress Read data2 Write data Read data Dat Memo bit Write data 0-15/sign32 Men reac xtend lw$to,200($s2) if Ss2=1000, it will load word in element number 1200 to sto
I type Instruction & Data stream rs rt rt Registers Read reg. address1 Read reg. address2 Write reg. address Write data Read data1 Read data2 ALU result ALU Zero 4 RegWrite ALU operation control address Write data Read data Sign extend op(6) rs(5) rt(5) Immediate data bit0-15 MenWrite MenRead 16 32 32bits data lw $t0, 200($s2) if $s2=1000，it will load word in element number 1200 to $t0 lw $t0, 200($s2) sw $t0, 200($s2) Data Memory ALUC ALUop
I type Instruction Data stream of beg PC+4 from instructiondatapath control To PC Shift left 2 I RewRite Branch b rs Read reg. address1 16-20 Read datal ALUop ALEC rt Read reg. address2 Registers ALU operation rite reg. ac Read data2 Write data d resul 16 Sign 32 0-15 extend
I type Instruction & Data stream of beq rs rt Registers Read reg. address1 Read reg. address2 Write reg. address Write data Read data1 Read data2 ALU result Zero ALU 4 RegWrite ALU operation Sign extend op(6) rs(5) rt(5) offset bit0-15 16 32 Shift left 2 PC+4 from instructiondatapath ADD control To PC ALUC Branch ALUop
J type Instruction 2s0并#00 PC+431:28]##bit25.0#00 ## Shift left To PC PC+4|31:28 25-00 control b left 2 RewRite B ranch rs Read reg. address1 6 20 Read datal rt Read reg. address2 4 Registers alU operation rite reg. add Read data2 Write data ALU resul 16 Si 32 0-15 gn J Loop xten
J type Instruction rs rt Registers Read reg. address1 Read reg. address2 Write reg. address Write data Read data1 Read data2 ALU result Zero ALU 4 RegWrite ALU operation Sign extend op(6) rs(5) rt(5) offset bit0-15 16 32 Shift left 2 ADD To PC control Branch PC+4[31:28]##bit25-00##00 bit25-00 Shift left 2 ## 28 PC+4[31:28] bit25-00##00 J Loop
4.合并数据通路 注:该通路不包含跳 转指令的实现 TC M Add Add ALU Rewrite Shift left 2 Instruis 25: 211 Read MemWrite address register 1 Read Instr r06 Read data 1 ALUSrC Instruction register 2 Zero MemtoReg 31:0] ALU Write Read Address Instruction nstrulrd 15: 1 X register data 2 result data memory Write Mux0 gust data Register Data Write memory Write register# selection [15:0] Sig extend ALU control MemRead 比较: ALU control bits add sto, st1, st2 from [5: 07 Instruction (5: 0 Funct! ALUOp w$t0,4($t1)
30 4. 合并数据通路 ALU control bits from I[5:0] Write register # selection rs rt rd imm 比较: add $t0,$t1,$t2 lw $t0,4($t1) Funct! 注：该通路不包含跳 转指令的实现