1/O Hardware overview o How can the processor command controller? Controller has one or more registers for data and control signals. The processor communicates with the controller by reading and writing bit patterns in the registers. o Two communication techniques: Direct l/O instructions Access the port address Each port typically contains of four registers,i.e.,status,control, data-in and data-out. Instructions:In,out ②Memory-mapped I/o Example:Oxa0000~Oxfffff are reserved to ISA graphics cards and BIOS routines Some systems use both techniques:PC as an example. 口18，走卡1，月00 陈话兰xlanchen@ustc.edu.cn http/staff.u0117401 Operating System操作系统原理斐 May22,20196/54
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Hardware overview How can the processor command controller? ▶ Controller has one or more registers for data and control signals. ▶ The processor communicates with the controller by reading and writing bit patterns in the registers. Two communication techniques: 1 Direct I/O instructions ⋆ Access the port address ⋆ Each port typically contains of four registers, i.e., status, control, data-in and data-out. ⋆ Instructions: In, out 2 Memory-mapped I/O ⋆ Example: 0xa0000 ~ 0xfffff are reserved to ISA graphics cards and BIOS routines ▶ Some systems use both techniques: PC as an example. 陈香兰 xlanchen@ustc.edu.cn http://staff.ustc.edu.cn/~xlanchen (Computer Application Laboratory, CS, USTC @ Hefei Embedded System Laboratory, CS, USTC @ Suzhou) 0117401: Operating System 操作系统原理与设计 May 22, 2019 6 / 54
I/O Hardware overview 1/O address range Device l/O Port Locations on PCs(partial) I/O address range device (hexadecimal) 000-00F DMA controller 020-021 interrupt controller 040-043 timer 200-20F game controller 2F8-2FF serial port(secondary) 320-32F hard-disk controller 378-37F parallel port 3D0-3DF graphics controller 3F0-3F7 diskette-drive controller 3F8-3FF serial port(primary) 东香兰xlanchen@ustc,edu.cn http:/staff..u011740i:Operating System操作系统原理 May22,20196/54
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Hardware overview I/O address range Device I/O Port Locations on PCs (partial) I/O address range device (hexadecimal) 000-00F DMA controller 020-021 interrupt controller 040-043 timer 200-20F game controller 2F8-2FF serial port (secondary) 320-32F hard-disk controller 378-37F parallel port 3D0-3DF graphics controller 3F0-3F7 diskette-drive controller 3F8-3FF serial port (primary) 陈香兰 xlanchen@ustc.edu.cn http://staff.ustc.edu.cn/~xlanchen (Computer Application Laboratory, CS, USTC @ Hefei Embedded System Laboratory, CS, USTC @ Suzhou) 0117401: Operating System 操作系统原理与设计 May 22, 2019 6 / 54
1/O Control Methods ●Polling(轮询方式) ②Interrupts(中断方式) ODMA(DMA方式) O(在汤书上：还有通道的概念) 口1⊙生年12月00 陈话兰xlanchen@ustc.edu.cn http/staff.u0117401 Operating System操作系统原理斐 May22,20197/54
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Control Methods 1 Polling (轮询方式) 2 Interrupts (中断方式) 3 DMA (DMA方式) 4 (在汤书上：还有通道的概念) 陈香兰 xlanchen@ustc.edu.cn http://staff.ustc.edu.cn/~xlanchen (Computer Application Laboratory, CS, USTC @ Hefei Embedded System Laboratory, CS, USTC @ Suzhou) 0117401: Operating System 操作系统原理与设计 May 22, 2019 7 / 54
Outline I/O Hardware and I/O control methods ●Polling(轮询方式) o Interrupts(中断方式) Direct Memory Access(DMA方式 o 1/O hardware summary 口1⊙生年12月00 东香兰xlanchen@ustc,edu.cn http:/staff..u0117401:Operating System操作系统原理 May22,20198/54
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outline 1 I/O Hardware and I/O control methods Polling (轮询方式) Interrupts (中断方式) Direct Memory Access (DMA方式) I/O hardware summary 陈香兰 xlanchen@ustc.edu.cn http://staff.ustc.edu.cn/~xlanchen (Computer Application Laboratory, CS, USTC @ Hefei Embedded System Laboratory, CS, USTC @ Suzhou) 0117401: Operating System 操作系统原理与设计 May 22, 2019 8 / 54
Polling(轮询方式) o Need handshaking(握手) o State of device command-ready In command register 1:a command is available for the controller busy In status register *0:ready for the next command;1:busy ③Error To indicate whether an l/O is ok. 口1⊙生年12月0C 陈话兰xlanchen@ustc.edu.cn http/staff.u0117401 Operating System操作系统原理斐 May22,20199/54
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Polling (轮询方式) Need handshaking (握手) State of device 1 command-ready ⋆ In command register ⋆ 1: a command is available for the controller 2 busy ⋆ In status register ⋆ 0: ready for the next command; 1: busy 3 Error ⋆ To indicate whether an I/O is ok. 陈香兰 xlanchen@ustc.edu.cn http://staff.ustc.edu.cn/~xlanchen (Computer Application Laboratory, CS, USTC @ Hefei Embedded System Laboratory, CS, USTC @ Suzhou) 0117401: Operating System 操作系统原理与设计 May 22, 2019 9 / 54