52同步时序电路设计尖践 e.g. 1 T-bird Tail Lights o Digital Design: 7.5: 7.6: 7.7: 7.8 ◆雷鸟车尾灯 ◆同步时序电路设计流程 每边各有3个灯:轮流顺序亮起,表示车的转向 ●原始状态转移图,状态化简和编码 ●三个输入:左转:右转:应急闪烁输入 ●建立状态转移输出表 ◆功能 ●导出状态方程、激励方程和输出方程 ●转向状态:6个灯轮流协调闪炼 ●画时序电路逻辑图 ●告警状态 ●检查电路:避免挂起(该步骤有时可省略 ◆同步时序电路设计方法 ●逻辑电路 圆■圆 ●VHDL描述 ZOTTFFS e.g.1 T-bird Tail Lights ou ::::: e.g.1 T-bird Tail Lights ;;;。8 Output Tabl State LC LB LA RA RB RC IDLE000000 L1001000 0000 左工了右 000110 0001 转 转 LR31111 凸凸凸凸凸凸 左Lc-1 3 LA RA RB RC右 转回回[[转 e.g.1 T-bird Tail Lights e.g.1 T-bird Tail Lights ◆8状态 ◆状态图完善1 ●原始图有问题 ●左转,右转 无法处理多输入(L3 ●HAZ告警,且 有效的情形 同时左转和右 转不清醒 (L+R+H)( Idle Tab (L+R+H) H+L,R E0。000 L RH
1 4 5.2 同步时序电路设计实践 Digital Design: 7.5; 7.6; 7.7; 7.8 同步时序电路设计流程 z 原始状态转移图，状态化简和编码 z 建立状态转移/输出表 z 导出状态方程、激励方程和输出方程 z 画时序电路逻辑图 z 检查电路：避免挂起 (该步骤有时可省略) 同步时序电路设计方法 z 逻辑电路 z VHDL描述 5 e.g.1 T-bird Tail Lights 雷鸟车尾灯 z 每边各有3个灯：轮流顺序亮起，表示车的转向 z 三个输入：左转；右转；应急闪烁输入 功能 z 转向状态：6个灯轮流协调闪烁 z 告警状态 6 e.g.1 T-bird Tail Lights LC LB LA 左 转 RA RB RC 右 转 7 e.g.1 T-bird Tail Lights 左 LC LB LA 转 RA RB RC 右 转 8 e.g.1 T-bird Tail Lights 8状态 z原始图有问题 无法处理多输入 有效的情形 LR3 Left Idle R1 R2 R3 L1 L2 L3 Right 1 1 1 1 1 1 (L+R+H)’ 1 HAZ 9 e.g.1 T-bird Tail Lights 状态图完善1 z左转，右转 zHAZ告警，且 同时左转和右 转……不清醒 LR3 L⋅R’⋅H’ Idle R1 R2 R3 L1 L2 L3 1 1 1 1 1 1 1 H+L⋅R L’⋅R⋅H’ (L+R+H)’
e.g. 1 T-bird Tail Lights e.91 T-bird Tail Lights(筒化的状态 ◆状态图完善2 ◆状态方程 意完备性! ●一有可能就进 Q=2212。(HA2+Rig 入告警模式 +Q2Q·HLAz+Q2Q 较安全 LR. ●状态图修改2 c"=g2Q1HAz·(Lef⊕Rghr L+R+H Idl H+LR +0,Q- HAZ L∵R,H ◆转换为激励方程 ◆逻辑电路 VHDL for theT-bird Tail Lights VHDL(Cont, oess(CLOCK) Use IEEE std_logic_1164.all Entity Abird is SET =1"then Lights < IDLE: else /End: HTS: buffer st L en, Right, HAz in Std LLC LB LARARBRI s when IDLE = If HAZ=1or(Left=" and Right='1) the Vbird arch of vtbird is 日G比 ⊥ Logic Vector(1to6) when L2 = > if HAZ='1 then Lights <= LR3; else Lights c L3: end if: nnnnm tO 油面RHA下比c比R比R LR3 => LIGHTS <E IDLE. Constant LR3 Std Logic Vector (1 to 6) ="111111. 小 eg2猜谜游戏 ◆完全描述的同步时序电路 ◆同步状态机 ● ●确定状态图 ·4个按钮,与输入G1~G4联接 1个ERR输出,与红色指示灯联扫 ◆非完全描述的同步时序电路 ·4个输出,与指示灯L1-L4联接,并与对应输入相邻 ●确定状态图 ◆功能 按设计需求,更改状态图,确定合理的状态转移 ●正常情况下,每经过1个时钟,模式旋转1个位置 >最小风险:使成为全喷定的状态图 ●时钟频率4Hz 最小成本:使成为光全确定的状态图 ●猜谜:按下1个按钮,某输 时钟触发沿到来前有效的灯 效,未能猜中:若相同为猜中。一旦 停止并且ERR输出会维持1个或多个时钟周期,直到输 入G取消,游戏继续进行
2 10 e.g.1 T-bird Tail Lights 状态图完善2 z一有可能就进 入告警模式比 较安全 z状态图修改2 LR3 L⋅R’⋅H’ Idle R1 R2 R3 L1 L2 L3 1 1 1 1 1 1 1 H+L⋅R L’⋅R⋅H’ (L+R+H)’ H H H H H’ H’ H’ H’ 12 e.g.1 T-bird Tail Lights 状态方程 转换为激励方程 逻辑电路… 1 2 210 2 0 20 ( ) n Q Q Q Q HAZ Right Q Q HAZ Q Q + = ⋅⋅⋅ + +⋅⋅ +⋅ Q Q HAZ n = ⋅ + 0 1 1 1 0 21 1 0 ( ) n Q Q Q HAZ Left Right Q Q HAZ + = ⋅⋅ ⋅ ⊕ +⋅⋅ 简化的状态 转移表 注意完备性! 13 VHDL for theT-bird Tail Lights Library IEEE; Use IEEE.std_logic_1164.all; Entity Vtbird is port ( Clock, Reset, Left, Right, HAZ: in Std_Logic; LIGHTS: buffer Std_Logic _Vector (1 to 6) ); --LC LB LA RA RB RC End; Architecture Vtbird_arch of Vtbird is Constant Idle : Std_Logic _Vector (1 to 6) := "000000"; Constant L1 : Std_Logic _Vector (1 to 6) := “001000"; Constant L2 : Std_Logic _Vector (1 to 6) := “011000"; Constant L3 : Std_Logic _Vector (1 to 6) := "111000"; Constant R1 : Std_Logic _Vector (1 to 6) := "000100"; Constant R2 : Std_Logic _Vector (1 to 6) := "000110"; Constant R3 : Std_Logic _Vector (1 to 6) := "000111"; Constant LR3 : Std_Logic _Vector (1 to 6) := "111111"; 14 VHDL(Cont.) VHDL(Cont.) Begin Process (CLOCK) Begin If CLOCK'event and CLOCK = '1' then If RESET = '1' then Lights <= IDLE; else Case Lights is when IDLE => If HAZ='1' or (Left='1' and Right='1') then Lights <= LR3; Elsif Left ='1' then Lights <= L1; Elsif Right ='1' then Lights <= R1; End if; when L1 => if HAZ='1' then Lights <= LR3; else Lights <= L2; end if; when L2 => if HAZ='1' then Lights <= LR3; else Lights <= L3; end if; when L3 => LIGHTS <= IDLE; when R1 => if HAZ='1' then Lights <= LR3; else Lights <= R2; end if; when R2 => if HAZ='1' then Lights <= LR3; else Lights <= R3; end if; when R3 => LIGHTS <= IDLE; when LR3 => LIGHTS <= IDLE; when others => null; End case; End if; End if; End process; End Vtbird_arch; LR3 L⋅R’⋅H’ Idle R1 R2 R3 L1 L2 L3 1 1 1 H+L⋅R L’⋅R⋅H’ (L+R+H)’ H H H H H’ H’ H’ H’ LR3 L⋅R’⋅H’ Idle R1 R2 R3 L1 L2 L3 1 1 1 H+L⋅R L’⋅R⋅H’ (L+R+H)’ H H H H H’ H’ H’ H’ 15 小结 完全描述的同步时序电路 z确定状态图 非完全描述的同步时序电路 z确定状态图 z按设计需求，更改状态图，确定合理的状态转移 ¾最小风险：使成为完全确定的状态图 ¾最小成本： 使成为完全确定的状态图 16 e.g.2 猜谜游戏 同步状态机 z 4个按钮，与输入G1~G4联接 z 1个ERR输出，与红色指示灯联接 z 4个输出，与指示灯L1~L4联接，并与对应输入相邻 功能 z 正常情况下，每经过1个时钟，模式旋转1个位置 z 时钟频率4Hz z 猜谜：按下1个按钮，某输入Gi 有效；若当前输入数Gi 与 时钟触发沿到来前有效的灯输出(状态)不同，则ERR有 效，未能猜中；若相同为猜中。一旦完成1次猜测，游戏 停止并且ERR输出会维持1个或多个时钟周期，直到输 入Gi 取消，游戏继续进行 G1 G2 G3 G4 L1 L2 L3 L4 ERR
e.g. 2 Guessing Game e.g.2 Guessing Game ◆5状态 ◆6状态 无法指示猜测结 果是否正确 G1263G G1G2G3.G ◆使用者同时按下 多个按键 需克服并进入 G2 G3.Ga 6263 ERR状态 G+G GaG G1G2G3 Guessing Game Guessing Game ◆ Gray-Coded State Assignment圖 o Gray-Coded State Assignment Moore状态机,输出方程为 s301 ERRE 状态方程可转换为激励方程:略 sm::1 对此1: Output- Coded State Assign 对比1: Output- Coded State Assign QOutput-Coded State Assignment oOutput-Coded State Assignment ●也可以用输出作为状态变量 直接用输出作为状态变量,得到输出方程为 =L…,L, L2., ERR(G43G2)●方程组并不简 00 or,aayor .i3·L2LERR·(G4G3 单,但输出数 x"=l4l2l2,z1,ERR、GG3G2G)变少(50) ERR+=L4. L,L,L, 0090 G4+G2+G1) 9 +L4.,Lz.. ERR +1·L12L·ER(G3+G2+G) +·z21·ERRG4+G+G2+G)
3 17 e.g.2 Guessing Game 5状态 无法指示猜测结 果是否正确 使用者同时按下 多个按键 需克服并进入 ERR状态 Stop S1 S2 S3 S4 G1 ’ .G2’. G3’.G4’ G1+G2+G3+G4 G1+G2+G3+G4 G1+G2+G3+G4 G1+G2+G3+G G 4 1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1+G2+ G3+G4 18 e.g.2 Guessing Game 6状态 SErr S1 S2 S3 S4 G1 ’ .G2’.G3’.G4’ G1+G3+G4 G1+G2+G4 G1+G2+G3 G2+G3+G4 G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ SOK G1 ’ .G2.G3’.G4’ G1 ’ .G2’.G3.G4’ G1 ’ .G2’.G3’.G4 G1.G2’.G3’.G4’ G1+G2+ G3+G4 G1+G2+ G3+G4 G1 ’ .G2’.G3’.G4’ 20 Guessing Game Gray-Coded State Assignment 状态 Q2 Q1 Q0 S1 0 0 0 S2 0 0 1 S3 0 1 1 S4 0 1 0 SOK 1 0 0 SErr 1 0 1 21 Guessing Game Gray-Coded State Assignment zMoore状态机，输出方程为 z状态方程可转换为激励方程：略…… 2 1 0 1 L4 Q Q Q n = ⋅ ⋅ + 2 1 0 1 L3 Q Q Q n = ⋅ ⋅ + 2 1 0 1 L2 Q Q Q n = ⋅ ⋅ + 2 1 0 1 L1 Q Q Q n = ⋅ ⋅ + ERR Q2 Q1 Q0 = ⋅ ⋅ 状态 Q2 Q1 Q0 S1 0 0 0 S2 0 0 1 S3 0 1 1 S4 0 1 0 SOK 1 0 0 SErr 1 0 1 22 Output-Coded State Assignment z也可以用输出作为状态变量 对比1：Output-Coded State Assign. Output-Coded State Assign. 23 Output-Coded State Assignment z直接用输出作为状态变量，得到输出方程为 对比1：Output-Coded State Assign. Output-Coded State Assign. ( 4 3 2 1) 1 4 3 2 1 L2 L L L L ERR G G G G n = ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + 1 ( 4 3 2 1) 2 4 3 1 L3 L L L L ERR G G G G n = ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + 2 1 ( 4 3 2 1) 3 4 1 L4 L L L L ERR G G G G n = ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + 3 2 1 4 3 2 1 ( 4 3 2 1) 1 L1 L L L ERR L L L L G G G G n = ⋅ ⋅ ⋅ + ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + （ ） 1 4321 432 43 1 2 431 4 21 3 421 321 4 321 4321 4321 ( ) ( ) ( ) ( ) ( ) n ERR L L L L ERR G G G L L L L ERR G G G L L L L ERR G G G L L L L ERR G G G L L L L ERR G G G G + = ⋅⋅⋅⋅ ⋅ + + +⋅⋅⋅⋅ ⋅ + + +⋅⋅⋅⋅ ⋅ + + +⋅ ⋅ ⋅⋅ ⋅ + + +⋅⋅⋅⋅ ⋅ + + + z方程组并不简 单，但输出数 变少(5Æ0)
对比2: Unused states Treatment 对此2: Unused States Treatment uNused States Treatment oOutput-Coded State Assignment ●状态图有6个状态 ●限制:机器不小心进入“未用状态”,可以自动回 ●实际5个触发器有32个状态,未用状态作为“无关 到正常”状态 ●自由度:通过引入“无关项”,允许对逻辑电路作 Karnaugh Map化筒只能处理莓单问题“……艹 计算机化简:许多综合软件易处理大舰模 一定的简化— Minimal cost apporach 计但却无活处理无近 般需要设计者单独写一段处理代码:; :: 对比2; Unused States Treatment VHDL for the Guessing game Machine OOutput-Coded State Assignment Use IEEE std_logic_1164.all, Port( Clock, Reset, G1, G2, G3. G4 L1,L2,L3,L4,E Out STD Logic): Type Sreg_type is(ST, S2, S3, S4, SOK, SERR) ●输出简化,例如ERR=4(G+G+G2) 可以证明,最简或与+l2L1G4+G3+G) 1 when S L2 <=1 when Sreg 式”只需5项,较与或+L2·L:L-(G4+ 式"需16项来得简单+L4D2LG+G2+G) RR<="1 +LL,.I2-Lr-ERR-(G+G,G,+G) VHDL for the Guessing Game Machine Guessing Game If CLOCK'event and CLoCK=1 then SET-1 then Sreg <a SOK; else ●Noti when si> If G2=1 or G3*" or G4*1 then Sreg s SERR The original quessing game is easy to win after s2s If GrrorG3 minute of practice because the lamps cycle at a very consistent rate of 4Hz when S3=> If G1=1or G4=t' then triple the clock speed but allow the lamps to stay when sas>f Gier or G2etr' or G3=r then sg in each state for a random length of time The user truly must guess whether a given lamp when SOK I SERR = If G1=0 an will stay on long enough for the corresponding pushbutton to be pressed when others => Sreg <s S1 Add an enable input, which is driven by the End case: S,Huca a Linear Feedback Shift Register(LFSR) End vggame_ arch
4 24 Unused States Treatment z状态图有6个状态 z实际5个触发器有32个状态，未用状态作为“无关 状态” zKarnaugh Map化简：只能处理简单问题 z计算机化简：许多综合软件容易处理大规模设 计，但却无法处理 “无关项”； 一般需要设计者单独写一段处理代码 对比2：Unused States Treatment Unused States Treatment 25 Output-Coded State Assignment z限制：机器不小心进入“未用状态”，可以自动回 到“正常”状态 z自由度：通过引入“无关项”，允许对逻辑电路作 一定的简化——Minimal cost apporach 对比2：Unused States Treatment Unused States Treatment 26 Output-Coded State Assignment z输出简化, 例如 可以证明，最简“或与 式”只需5项，较“与或 式”需16项来得简单 1 14 3 2 1 2 4 31 2 1 3 421 321 4 321 4321 4321 ( ) ( ) ( ) ( ) ( ) n ERR L G G G LL G G G LLL G G G LLLL G G G L L L L ERR G G G G + =⋅ + + +⋅⋅ + + +⋅ ⋅ ⋅ + + +⋅ ⋅ ⋅⋅ + + +⋅⋅⋅⋅ ⋅ + + + 对比2：Unused States Treatment Unused States Treatment 27 VHDL for the Guessing Game Machine Library IEEE; Use IEEE.std_logic_1164.all; Entity Vggame is Port ( Clock, Reset, G1, G2, G3, G4 : in STD_LOGIC; L1, L2, L3, L4, Err : out STD_LOGIC ); End; Architecture Vggame_arch of Vggame is Type Sreg_type is (S1, S2, S3, S4, SOK, SERR); signal Sreg: Sreg_type; Begin L1 <= '1' when Sreg = S1 else '0'; L2 <= '1' when Sreg = S2 else '0'; L3 <= '1' when Sreg = S3 else '0'; L4 <= '1' when Sreg = S4 else '0'; ERR <= '1' when Sreg = SERR else '0'; Process (CLOCK) Begin 28 If CLOCK'event and CLOCK = '1' then If RESET = '1' then Sreg <= SOK; else case Sreg is when S1 => If G2='1' or G3='1' or G4='1' then Sreg <= SERR; elsif G1='1' then Sreg <= SOK; else Sreg <= S2; End if; when S2 => If G1='1' or G3='1' or G4='1' then Sreg <= SERR; elsif G1='1' then Sreg <= SOK; else Sreg <= S3; End if; when S3 => If G1='1' or G2='1' or G4='1' then Sreg <= SERR; elsif G1='1' then Sreg <= SOK; else Sreg <= S4; End if; when S4 => If G1='1' or G2='1' or G3='1' then Sreg <= SERR; elsif G1='1' then Sreg <= SOK; else Sreg <= S1; End if; when SOK | SERR => If G1='0' and G2='0' and G3='0' and G4='0' then Sreg <= S1; End if; when others => Sreg <= S1; End case; End If; End If; End process; End Vggame_arch; SErr S1 S2 S3 S4 G1 ’ .G2’.G3’.G4’ G1+G3+G4 G1+G2+G4 G1+G2+G3 G2+G3+G4 G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ SOK G1 ’ .G2.G3’.G4’ G1 ’ .G2’.G3.G4’ G1 ’ .G2’.G3’.G4 G1.G2’.G3’.G4’ G1+G2+ G3+G4 G1 ’ .G2’.G3’.G4’ SErr S1 S2 S3 S4 G1 ’ .G2’.G3’.G4’ G1+G3+G4 G1+G2+G4 G1+G2+G3 G2+G3+G4 G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ SOK G1 ’ .G2.G3’.G4’ G1 ’ .G2’.G3.G4’ G1 ’ .G2’.G3’.G4 G1.G2’.G3’.G4’ G1+G2+ G3+G4 G1 ’ .G2’.G3’.G4’ VHDL for the Guessing Game Machine 29 Guessing Game Noting zThe original guessing game is easy to win after a minute of practice because the lamps cycle at a very consistent rate of 4Hz zTo make it more challenging, we can double or triple the clock speed but allow the lamps to stay in each state for a random length of time zThe user truly must guess whether a given lamp will stay on long enough for the corresponding pushbutton to be pressed zAdd an enable input, which is driven by the output of a pseudorandom sequence generator, a Linear Feedback Shift Register (LFSR)
e.g. 3 Traffic Light Controller+ 5.3 Sequential Logic DesignA18 Digital Design: 8.1: 8.8: 8.9 Timing Diagrams Specifications Synchronizer Failure and Metastability o Traffic sensors and signals in an intersection. sunnyvale, California 5.3 Timing Diagrams Specifications 5.3 Timing diagrams ◆ Timing Diagram ◆ Set-up time margin XXXXXXXX XXX XXXXXXXX ∝ XXXXXXXXXXX Flip-Flop XXXXXXXXXXXXXX Set-up time margin t-td(max -tomb(max tsu, must be greate Timing Diagrams Impediments to Sync. Design ◆ Hold time margin ◆ Clock skew CLOCK tpd(Min)+comb(Min -th-tskew(max) >0 Q1 XXXXXXXX XXXXXXXXXXXXX Hold time margin tpd(Min +comb(Min th, must be greater than A long slow path: skew 5
5 30 e.g.3 Traffic Light Controller自学 Traffic sensors and signals in an intersection, Sunnyvale, California 40 5.3 Sequential Logic DesignA18 Digital Design: 8.1; 8.8; 8.9 z Timing Diagrams & Specifications z Impediments to Synchronous Design z Synchronizer Failure and Metastability 41 5.3 Timing Diagrams & Specifications Timing Diagram tclk tsu th tcomb tpd tpd CLOCK Flip-Flop outputs Combinational outputs Flip-Flop Inputs 42 5.3 Timing Diagrams & Specifications Set-up time margin z Set-up time margin tclk-tpd(max)-tcomb(max)-tsu , must be greater than 0 tclk Setup-time margin tsu th tcomb tpd tpd CLOCK Flip-Flop outputs Combinational outputs Flip-Flop Inputs 43 Timing Diagrams Hold time margin z Hold time margin tpd(Min)+tcomb(Min)-th , must be greater than 0 Hold-time margin CLOCK tpd Flip-Flop outputs Combinational outputs Flip-Flop Inputs tclk tsu th tcomb tpd 45 Impediments to Sync. Design* Clock Skew In CP D Q D Q A B Q1 Q2 A long slow path: tskew tpd(Min)+tcomb(Min)-th -tskew(max) >0 tpd(Min)+tcomb(Min)-th>0 Comb