Return Example demo -reth.ys 0x000: asImoV1 Stack,号esp#工 nitia1 ize stack pointer 0x006: callp i Procedure call 0x001: irmovl 5 esi Return point 0x011: ha1七 0x020:.p。s0x20 0x020: p: irmovl $-1, edi procedure 0x026 e七 0x027 im。v1勺1,号eax f Should not be executed 0x02a: im。v12,号ecx f Should not be executed 0x033: imov13,号edx f should not be executed 0x039: irmovl $4 ebx i Should not be executed 0x100:.pos0x100 0x100: Stack Stack: Stack pointer a Previously executed three additional instructions Processor
– 11 – Processor 0x000: irmovl Stack,%esp # Initialize stack pointer 0x006: call p # Procedure call 0x00b: irmovl $5,%esi # Return point 0x011: halt 0x020: .pos 0x20 0x020: p: irmovl $-1,%edi # procedure 0x026: ret 0x027: irmovl $1,%eax # Should not be executed 0x02d: irmovl $2,%ecx # Should not be executed 0x033: irmovl $3,%edx # Should not be executed 0x039: irmovl $4,%ebx # Should not be executed 0x100: .pos 0x100 0x100: Stack: # Stack: Stack pointer Return Example ◼ Previously executed three additional instructions demo-retb.ys
Correct Return Example i demo -retb 0x026 ret LFIDIEMIW bubble FDE MW FDEMW bubble F E M W 0x00b irmo1S5,号esi# Return F E M W Fiqure 4.61 P344 ■ As ret passes through pipeline, stall at fetch stage valM =OxO e While in decode execute, and memory stage fetch the same instruction after ret 3 times Inject bubble into decode vaC←5 stage rB←告esi a Release stall when reach write-back stage Processor
– 12 – Processor 0x026: ret F D E M bubble F D E M W W bubble F D E M W bubble F D E M W 0x00b: irmovl $5,%esi # Return F D E M W # demo-retb F D E M W F valC 5 rB %esi F valC 5 rB %esi W valM = 0x0b • • • Correct Return Example ◼ As ret passes through pipeline, stall at fetch stage ⚫ While in decode, execute, and memory stage ⚫ fetch the same instruction after ret 3 times. ◼ Inject bubble into decode stage ◼ Release stall when reach write-back stage Figure 4.61 P344
Detecting Return icode valA dstE dstM Execute icode ifun valA valB Sel+Fwd Fwd Decode w vaIN D looe un iA e vac vap Condition Trigger Processing ret IRET in(D icode, E_icode, M_icode] Figure 4.64 P347 Processor
– 13 – Processor Detecting Return Condition Trigger Processing ret IRET in { D_icode, E_icode, M_icode } M D Register file CC ALU rB dstE dstM ALU A ALU B srcA srcB ALU fun. Decode Execute A B M E W _valM W _valE icode Bch valE valA dstE dstM E icode ifun valC valA valB dstE dstM srcA srcB icode ifun rA valC valP d_srcA d_srcB e_Bch M_Bch Sel+Fwd A Fwd B M_valE e_valE Figure 4.64 P347
Control for Return i demo -retb 0x026 ret F D E M W bubble F DE MI W bubble LF⊥DEMW bubble F W 0x00b irmovl $5, esi Return LFLDIEMIW Condition E M Processing ret stall bubble normal normal normal Fiqure 4.66 P348 Processor
– 14 – Processor 0x026: ret F D E M bubble F D E M W W bubble F D E M W bubble F D E M W 0x00b: irmovl $5,%esi # Return F D E M W # demo-retb F D E M W Control for Return Condition F D E M W Processing ret stall bubble normal normal normal Figure 4.66 P348