Asynchrono Flags RAM Shift FIGURE 81.27 The register family bus in a microprocessor or other bus-based system and that is used to describe the microprocessor. The Z80, for instance, is said to be an eight-bit processor, indicating that the working registers are eight bits wide. The bit values in the register may represent a numerical value in standard fixed point binary, floating point, or some other coded form. Alternatively, they may indicate some logical pattern such as the settings of switches used in an industrial controller In order to control when the flip-flops set or reset we must make use of synchronous flip-flops, leaving the D or J-K inputs to determine what the flip-flop is to do logically, that is to set or reset. In all bus-organized systems it is necessary to control when the data held in the register is fed on to the output bus. This is usually achieved by means of three-state(3S)gates at the register outputs which are disabled, that is, set to their high e state, until the data A multi-register, bus-structured digital system will have the nth bit of each register connected to bit n of the data bus at both the input and output of the register. In order to transfer data from one register to another, or, more strictly, to transfer a copy of the contents of one register to another register, the output gates of the source register must be enabled so that the data is fed on to the bus. This data becomes available at the inputs of all registers and is latched in under the control of the appropriate input signals. It is important in the desig of the sequencing circuitry that only one set of register output gates can be enabled at any time, although the data can be latched into as many registers as required The signal controlling the input to the register is applied to all flip-flops simultaneously and its action depends on the type of flip-flop used Edge-triggered flip-flops set or reset according to the value on the data inputs at the time the control signal changes. These registers are sometimes known as staticizer. After the few nanosec- onds required for the flip-flops to settle to their new values, the register content is available at the output gating The correct operation of the circuitry depends upon certain timing criteria being satisfied and minimum values are quoted by the manufacturers. Each is the smallest time above which the device is guaranteed to operate correctly, but in practice the device probably functions satisfactorily with smaller time intervals on at least some of the parameters. The main timing constraints occur at the inputs to the flip-flops and are illustrated in Fig 81.28. The interval preceding the active transition of the control input is the setup time, t,, during which the data signal must be held steady; th is the hold time and is the interval during which the data signal must be retained following the active transition of the control input; tw is a minimum pulse width indication which applies to the control inputs such as the clock, reset, and clear. The clock pulse width is usually quoted both for the high state and for the low and is related to the maximum clocking frequency of the flip-flops used in the e 2000 by CRC Press LLC
© 2000 by CRC Press LLC bus in a microprocessor or other bus-based system and that is used to describe the microprocessor. The Z80, for instance, is said to be an eight-bit processor, indicating that the working registers are eight bits wide. The bit values in the register may represent a numerical value in standard fixed point binary, floating point, or some other coded form. Alternatively, they may indicate some logical pattern such as the settings of switches used in an industrial controller. In order to control when the flip-flops set or reset we must make use of synchronous flip-flops, leaving the D or J-K inputs to determine what the flip-flop is to do logically, that is to set or reset. In all bus-organized systems it is necessary to control when the data held in the register is fed on to the output bus. This is usually achieved by means of three-state (3S) gates at the register outputs which are disabled, that is, set to their highimpedance state, until the data is required. A multi-register, bus-structured digital system will have the nth bit of each register connected to bit n of the data bus at both the input and output of the register. In order to transfer data from one register to another, or, more strictly, to transfer a copy of the contents of one register to another register, the output gates of the source register must be enabled so that the data is fed on to the bus. This data becomes available at the inputs of all registers and is latched in under the control of the appropriate input signals. It is important in the design of the sequencing circuitry that only one set of register output gates can be enabled at any time, although the data can be latched into as many registers as required. The signal controlling the input to the register is applied to all flip-flops simultaneously and its action depends on the type of flip-flop used. Edge-triggered flip-flops set or reset according to the value on the data inputs at the time the control signal changes. These registers are sometimes known as staticizers. After the few nanoseconds required for the flip-flops to settle to their new values, the register content is available at the output gating. The correct operation of the circuitry depends upon certain timing criteria being satisfied and minimum values are quoted by the manufacturers. Each is the smallest time above which the device is guaranteed to operate correctly, but in practice the device probably functions satisfactorily with smaller time intervals on at least some of the parameters. The main timing constraints occur at the inputs to the flip-flops and are illustrated in Fig. 81.28. The interval preceding the active transition of the control input is the setup time, tsu, during which the data signal must be held steady; th is the hold time and is the interval during which the data signal must be retained following the active transition of the control input; tw is a minimum pulse width indication which applies to the control inputs such as the clock, reset, and clear. The clock pulse width is usually quoted both for the high state and for the low and is related to the maximum clocking frequency of the flip-flops used in the register. FIGURE 81.27 The register family
Active Transition Timing/ Control Data Input IL ime→ FIGURE 81.28 Control timing parameters. An alternative flip-flop is the transparent latch, an interesting development of the simple latch. When enabled a control signal, C, by setting C high or1", the latch becomes a transparent section of the data path and the data value at the input simply reappears at the output. When the control signal disables the latch, that is C is low or0", however, the last value applied to the latch is "frozen"and held until the control signal is taken high again. The 74LS373, Fig. 81. 29(a), consists of eight transparent latches with a common control input labeled ENABLE. The 74LS374, Fig. 81. 29(b), is a typical eight-bit register using positive edge-triggering for all flip-flops. It includes 3S output gates designed specifically for driving highly capacitive loads, such as are found in bus-organized systems, and which respond to an output control signal operating quite independently of the flip-flops. Typical minimum timing figures for the 74LS373 and 74LS374 are shown in Fig. 81. 29(c)and the waveforms occurring for the two different types of register are illustrated in Fig. 81.29(d) An extended form of transparent operation is provided in addressable latches such as the eight-bit 74LS259 well as being able to store successive bits arriving at a single input, D, in the eight addressable latches, using a three-bit address, any latch can be selected for output so that the device can also act as a 1-of-8 decoder or demultiplexer. Four modes of operation are possible under the control of the enable and clear inputs In the addressable latch mode the single-addressed latch acts transparently, with all other latches retaining their previous states. When in the memory mode all latches retain their previous states and are unaffected by address the decode mode the output of the addressed latch follows the level at the D input, and in the clear mode all outputs are set low Shift Registers There are essentially two modes of operation for a register, either serial or parallel, and those we have considered far have operated in parallel mode. Parallel operation affects the entire group of bits held in the register during a single clock pulse In serial operation data bits are inputted(or outputted)sequentially to(or from) the register, one bit for every clock pulse. A register which has the facility to move the stored bits one place at a time left or right under the control of the clock pulse is called a shift register(Fig. 81.30) is Shift registers are normally implemented by means of D, S-R or J-K flip-flops. As an example, the 74LS165A shown(Fig. 81.31), consisting of eight S-R-type flip-flops with clock, clock inhibit, and shift/load control inputs. The different functions are tabulated in Fig. 81.32 Data presented to the eight separate inputs is loaded into the register in parallel when the shift/load input is taken low. Shifting occurs when the shift/load input is high and the clock pulse is applied, the action taking place on the low-to-high transition of the clock pulse. Registers are available which switch on the other clock the 74LS295A, which is a four-bit shift register with serial and parallel operating modes, carries out all data transfers and shifting operations on the high-to-low clock transition. This device also rovides 3S operation. Selection of the mode of operation is carried out by suitable combinations of the MODE SELECT inputs Large-capacity shift registers make use of charge-coupled devices(CCD). These are MOS devices in which data bits are stored dynamically as charge between gate and substrate on what is effectively a distributed multi-gate e 2000 by CRC Press LLC
© 2000 by CRC Press LLC An alternative flip-flop is the transparent latch, an interesting development of the simple latch.When enabled by a control signal, C, by setting C high or “1”, the latch becomes a transparent section of the data path and the data value at the input simply reappears at the output. When the control signal disables the latch, that is C is low or “0”, however, the last value applied to the latch is “frozen” and held until the control signal is taken high again. The 74LS373, Fig. 81.29(a), consists of eight transparent latches with a common control input labeled ENABLE. The 74LS374, Fig. 81.29(b), is a typical eight-bit register using positive edge-triggering for all flip-flops. It includes 3S output gates designed specifically for driving highly capacitive loads, such as are found in bus-organized systems, and which respond to an output control signal operating quite independently of the flip-flops. Typical minimum timing figures for the 74LS373 and 74LS374 are shown in Fig. 81.29(c) and the waveforms occurring for the two different types of register are illustrated in Fig. 81.29(d). An extended form of transparent operation is provided in addressable latches such as the eight-bit 74LS259. As well as being able to store successive bits arriving at a single input, D, in the eight addressable latches, using a three-bit address, any latch can be selected for output so that the device can also act as a 1-of-8 decoder or demultiplexer. Four modes of operation are possible under the control of the enable and clear inputs. In the addressable latch mode the single-addressed latch acts transparently, with all other latches retaining their previous states. When in the memory mode all latches retain their previous states and are unaffected by address or data inputs. In the decode mode the output of the addressed latch follows the level at the D input, and in the clear mode all outputs are set low. Shift Registers There are essentially two modes of operation for a register, either serial or parallel, and those we have considered so far have operated in parallel mode. Parallel operation affects the entire group of bits held in the register during a single clock pulse. In serial operation data bits are inputted (or outputted) sequentially to (or from) the register, one bit for every clock pulse. A register which has the facility to move the stored bits one place at a time left or right under the control of the clock pulse is called a shift register (Fig. 81.30). Shift registers are normally implemented by means of D, S-R or J-K flip-flops. As an example, the 74LS165A is shown (Fig. 81.31), consisting of eight S-R-type flip-flops with clock, clock inhibit, and shift/load control inputs. The different functions are tabulated in Fig. 81.32. Data presented to the eight separate inputs is loaded into the register in parallel when the shift/load input is taken low. Shifting occurs when the shift/load input is high and the clock pulse is applied, the action taking place on the low-to-high transition of the clock pulse. Registers are available which switch on the other clock edge. For example, the 74LS295A, which is a four-bit shift register with serial and parallel operating modes, carries out all data transfers and shifting operations on the high-to-low clock transition. This device also provides 3S operation. Selection of the mode of operation is carried out by suitable combinations of the MODE SELECT inputs. Large-capacity shift registers make use of charge-coupled devices (CCD). These are MOS devices in which data bits are stored dynamically as charge between gate and substrate on what is effectively a distributed multi-gate FIGURE 81.28 Control timing parameters