D Cb A FIGURE 81.21 PROM logic circuit. Sequential Logic Circuits A sequential logic circuit is a circuit that has feedback such that the output signals of the circuit are functions of all or part of the present state output signals of the circuit in addition to any external input signals to the circuit. The vast majority of sequential logic circuits designed for industrial applications are synchronous or clock-mode circuits Synchronous Sequential Logic Circuits Synchronous sequential logic circuits change states only at the rising or falling edge of the smra logic circuit signal. To allow proper circuit operation, any external input signals to the synchronous sequent must generate excitation inputs that occur with the proper setup time(t,)and hold time(th) requirements relative to the designated clock edge for the memory elements being used. Synchronous or clock-mode sequen tial logic circuits depend on the present state of memory devices called bistables or flip-flops(asynchronou sequential logic circuits) that are driven by a system clock as illustrated by the synchronous sequential logic circuit in Fig. 81.23 with the availability of edge-triggered D flip-flops and edge-triggered J-Kflip-flops in IC packages, a designer can choose which flip-flop type to use as the memory devices in the memory section of a synchronous sequential logic circuit. Many designers prefer to design with edge-triggered D flip-flops rather than edge-triggered J-K p-flops because D flip-flops are (a)more cost efficient, (b) easier to design with, and(c) more convenient since many of the available Pal devices incorporate edge-triggered D flip-flops in the output section of their architectures. PAL devices that contain flip-flops in their output section are referred to as registered PALs(or, in general, registered PLDs). The synchronous sequential logic circuit shown in Fig. 81.24 using edge-triggered D flip-flops functionally performs the same as the circuit in Fig. 81.23. e 2000 by CRC Press LLC
© 2000 by CRC Press LLC Sequential Logic Circuits A sequential logic circuit is a circuit that has feedback such that the output signals of the circuit are functions of all or part of the present state output signals of the circuit in addition to any external input signals to the circuit. The vast majority of sequential logic circuits designed for industrial applications are synchronous or clock-mode circuits. Synchronous Sequential Logic Circuits Synchronous sequential logic circuits change states only at the rising or falling edge of the synchronous clock signal. To allow proper circuit operation, any external input signals to the synchronous sequential logic circuit must generate excitation inputs that occur with the proper setup time (tsu) and hold time (th) requirements relative to the designated clock edge for the memory elements being used. Synchronous or clock-mode sequential logic circuits depend on the present state of memory devices called bistables or flip-flops (asynchronous sequential logic circuits) that are driven by a system clock as illustrated by the synchronous sequential logic circuit in Fig. 81.23. With the availability of edge-triggered D flip-flops and edge-triggered J-K flip-flops in IC packages, a designer can choose which flip-flop type to use as the memory devices in the memory section of a synchronous sequential logic circuit. Many designers prefer to design with edge-triggered D flip-flops rather than edge-triggered J-K flip-flops because D flip-flops are (a) more cost efficient, (b) easier to design with, and (c) more convenient since many of the available PAL devices incorporate edge-triggered D flip-flops in the output section of their architectures. PAL devices that contain flip-flops in their output section are referred to as registered PALs (or, in general, registered PLDs). The synchronous sequential logic circuit shown in Fig. 81.24 using edge-triggered D flip-flops functionally performs the same as the circuit in Fig. 81.23. FIGURE 81.21 PROM logic circuit
T ■T FIGURE 81.22 PALl6L8 implementation for the binary to seven-segment hexadecimal character generator. Source: PAL Device Data Book, Advanced Micro Devices, Sunnyvale, Calif, 1988, P. 5-46.) Notice that in general more combinational logic gates will be required for D flip-flop implementations ompared to J-K flip-flop implementations of the same synchronous sequential function. Using a registered PAL such as a PALI6RP4A would only require one IC package to implement the circuit in Fig. 81.24. The PAL16RP4A has four edge-triggered D flip-flops in its output section, of which only two are required for this design. Generally speaking, synchronous sequential logic circuits can be designed much more easily(considering design time as the criteria)than fundamental-mode asynchronous sequential logic circuits with a system clock and edge-triggered flip-flops, a designer does not have to worry about hazards or glitches(momentary error conditions that occur at the outputs of combinational logic circuits), since outputs are allowed to become stable before the next clock edge occurs. Thus, sequential logic circuit designs allow the use of combinational hazardou circuits as well as the use of arbitrary state assignments, provided the resulting combinational logic gate count e 2000 by CRC Press LLC
© 2000 by CRC Press LLC Notice that in general more combinational logic gates will be required for D flip-flop implementations compared to J-K flip-flop implementations of the same synchronous sequential function. Using a registered PAL such as a PAL16RP4A would only require one IC package to implement the circuit in Fig. 81.24. The PAL16RP4A has four edge-triggered D flip-flops in its output section, of which only two are required for this design. Generally speaking, synchronous sequential logic circuits can be designed much more easily (considering design time as the criteria) than fundamental-mode asynchronous sequential logic circuits. With a system clock and edge-triggered flip-flops, a designer does not have to worry about hazards or glitches (momentary error conditions that occur at the outputs of combinational logic circuits), since outputs are allowed to become stable before the next clock edge occurs. Thus, sequential logic circuit designs allow the use of combinational hazardous circuits as well as the use of arbitrary state assignments, provided the resulting combinational logic gate count or package count is acceptable. FIGURE 81.22 PAL16L8 implementation for the binary to seven-segment hexadecimal character generator. (Source: PAL Device Data Book, Advanced Micro Devices, Sunnyvale, Calif., 1988, p. 5–46.)
DC FIGURE 81.23 Synchronous sequential logic circuit using positive edge-triggered J-K flip-flo DC y1 y2 HC FIGURE 81.24 Synchronous sequential logic circuit using positive edge-triggered D flip-flops. IEEE symbol FIGURE 81.25 Fundamental-mode asynchronous sequential logic circuit. Asynchronous Sequential Logic Circuits Asynchronous sequential logic circuits may change states any time a single input signal occurs(either a level change for a fundamental mode circuit or a pulse for a pulse mode circuit). No other input signal change (either level change or pulse) is allowed until the circuit reaches a stable internal state. Latches and edge triggered flip-flops are asynchronous sequential logic circuits and must be designed with care by utilizing hazard-free combinational logic circuits and race-free or critical race-free state assignments. Both hazards and race conditions interfere with the proper operation of asynchronous logic circuits. The gated D latch circuit e 2000 by CRC Press LLC
© 2000 by CRC Press LLC Asynchronous Sequential Logic Circuits Asynchronous sequential logic circuits may change states any time a single input signal occurs (either a level change for a fundamental mode circuit or a pulse for a pulse mode circuit). No other input signal change (either level change or pulse) is allowed until the circuit reaches a stable internal state. Latches and edgetriggered flip-flops are asynchronous sequential logic circuits and must be designed with care by utilizing hazard-free combinational logic circuits and race-free or critical race-free state assignments. Both hazards and race conditions interfere with the proper operation of asynchronous logic circuits. The gated D latch circuit FIGURE 81.23 Synchronous sequential logic circuit using positive edge-triggered J-K flip-flops. FIGURE 81.24 Synchronous sequential logic circuit using positive edge-triggered D flip-flops. FIGURE 81.25 Fundamental-mode asynchronous sequential logic circuit
FIGURE 81.26 Double- rank pulse- mode asynchronous sequential logic circuit lustrated in Fig. 81.25 is an example of a fundamental-mode asynchronous sequential logic circuit that is used extensively in microprocessor systems for the temporary storage of data Quad, octal, 9-bit, and 10-bit transparent latches are readily available as off-the-shelf IC devices for these types of applications For proper asynchronous circuit operation, the signal applied to the data input D of the fundamental-mode circuit in Fig. 81.25 must meet a minimum setup time and hold time requirement relative he control input C, changing the latch to the memory mode when C goes to 0. This is a basic requirement for asynchronous circuits with level inputs, i.e., only one input signal is allowed to change at one time. Another restriction requires letting the circuit reach a stable state before allowing the next input signal to change An example of a reliable pulse-mode asynchronous sequential logic circuit is shown in Fig. 81. 26. While the inputs to asynchronous fundamental-mode circuits are logic levels, the inputs to asynchronous pulse-mode circuits are pulses. Pulse-mode circuits have the restriction that the maximum pulse width of any input pulse must be sufficiently narrow such that an input pulse is no longer present when the new present state output signal becomes available. The purpose of the double-rank circuit in Fig. 81. 26 is to ensure that the maximum pulse width requirement is easily met, since the output is not fed back until the input pulse is removed, i.e Des low or goes to logic 0. The input signals to pulse-mode circuits must also meet the following res strictions only one input pulse may be applied at one time, (b)the circuit must be allowed to reach a new stable state before applying the next input pulse, and (c) the minimum pulse width of an input pulse is determined by the time it takes to change the slowest flip-flop used in the circuit to a new stable state Defining Terms Asynchronous circuit: A sequential logic circuit without a system clock. Combinational logic circuit: A circuit with external output signal(s)that are totally dependent on the external input signals applied to the circuit. Fan-out requirement: The maximum number of loads a device output can drive and still provide dependable I and 0 logic levels Hazard or glitch: A momentary output error that occurs in a logic circuit because of input signal propagation along different delay paths in the circuit. Hexadecimal: The name of the number system with a base or radix of 16 with the usual symbols of 0 9,A, B,C,, F. Medium-scale integration: A single packaged IC device with 12 to 99 gate-equivalent circuits Race-free state assignment: A state assignment made for asynchronous sequential logic circuits such that nore than a one-bit change occurs between each stable state transition, thus preventing possible critical races. Sequential logic circuit: A circuit with output signals that are dependent on all or part of the present state ut signals fed back as input signals as well as any external input signals if they should exist. Sum of products(SOP): A standard form for writing a Boolean equation that contains product terms(input rariables or signal names either complemented or uncomplemented ANDed together)that are logically summed(ORed together ). Synchronous or clock -mode circuit: A sequential logic circuit that is synchronized with a system clock. e 2000 by CRC Press LLC
© 2000 by CRC Press LLC illustrated in Fig. 81.25 is an example of a fundamental-mode asynchronous sequential logic circuit that is used extensively in microprocessor systems for the temporary storage of data. Quad, octal, 9-bit, and 10-bit transparent latches are readily available as off-the-shelf IC devices for these types of applications. For proper asynchronous circuit operation, the signal applied to the data input D of the fundamental-mode circuit in Fig. 81.25 must meet a minimum setup time and hold time requirement relative to the control input C, changing the latch to the memory mode when C goes to 0. This is a basic requirement for asynchronous circuits with level inputs, i.e., only one input signal is allowed to change at one time. Another restriction requires letting the circuit reach a stable state before allowing the next input signal to change. An example of a reliable pulse-mode asynchronous sequential logic circuit is shown in Fig. 81.26. While the inputs to asynchronous fundamental-mode circuits are logic levels, the inputs to asynchronous pulse-mode circuits are pulses. Pulse-mode circuits have the restriction that the maximum pulse width of any input pulse must be sufficiently narrow such that an input pulse is no longer present when the new present state output signal becomes available. The purpose of the double-rank circuit in Fig. 81.26 is to ensure that the maximum pulse width requirement is easily met, since the output is not fed back until the input pulse is removed, i.e., goes low or goes to logic 0. The input signals to pulse-mode circuits must also meet the following restrictions: (a) only one input pulse may be applied at one time, (b) the circuit must be allowed to reach a new stable state before applying the next input pulse, and (c) the minimum pulse width of an input pulse is determined by the time it takes to change the slowest flip-flop used in the circuit to a new stable state. Defining Terms Asynchronous circuit: A sequential logic circuit without a system clock. Combinational logic circuit: A circuit with external output signal(s) that are totally dependent on the external input signals applied to the circuit. Fan-out requirement: The maximum number of loads a device output can drive and still provide dependable 1 and 0 logic levels. Hazard or glitch: A momentary output error that occurs in a logic circuit because of input signal propagation along different delay paths in the circuit. Hexadecimal: The name of the number system with a base or radix of 16 with the usual symbols of 0 … 9,A,B,C,D,E,F. Medium-scale integration: A single packaged IC device with 12 to 99 gate-equivalent circuits. Race-free state assignment: A state assignment made for asynchronous sequential logic circuits such that no more than a one-bit change occurs between each stable state transition, thus preventing possible critical races. Sequential logic circuit: A circuit with output signals that are dependent on all or part of the present state output signals fed back as input signals as well as any external input signals if they should exist. Sum of products (SOP): A standard form for writing a Boolean equation that contains product terms (input variables or signal names either complemented or uncomplemented ANDed together) that are logically summed (ORed together). Synchronous or clock-mode circuit: A sequential logic circuit that is synchronized with a system clock. FIGURE 81.26 Double-rank pulse-mode asynchronous sequential logic circuit
elated Topic 79.2 Logic Gates(IC) Advanced Micro Devices, PAL Device Data Book, Sunnyvale, Calif. Advanced Micro Devices, Inc., 1988. ANSI/IEEE Std 91-1984, IEEE Standard Graphic Symbols for Logic Functions, New York: The Institute of Electrical nd Electronics Engineers, 1984 ANSI/IEEE Std 991-1986, IEEE Standard for Logic Circuit Diagrams, New York: The Institute of Electrical and Electronics Engineers, 1986 K J. Breeding, Digital Design Fundamentals, 2nd ed, Englewood Cliffs, N J. Prentice-Hall, 1992. E.J. Hill and G.R. Peterson, Introduction to Switching Theory d- Logical Design, 3rd ed, New York: John Wiley, M.M. Mano, Digital Design, 2nd ed, Englewood Cliffs, N] Prentice-Hall, 1991 E ]. McCluskey, Logic Design Principles, Englewood Cliffs, N J: Prentice-Hall, 1986 Minc, PLDesigner-XL, The Next Generation in Programmable Logic Synthesis, Version 3.5, User's Guide, Colorado Springs: Minc, Incorporated, 1996. R.S. Sandige, Modern Digital Design, New York: McGraw-Hill, 1990 Further information The monthly magazine IEEE Journal on Solid-State Circuits presents papers discussing logic circuits, for example, Automating the Design of Asynchronous Sequential Logic Circuits, in its March 1991 issue, Pp. 364-370. The monthly magazine IEEE Transactions on Computers presents papers discussing logic circuits, for example, Concurrent Logic Programming as a Hardware Descriptive Tool, "in its January 1990 issue, Pp. 72-88 Also, the monthly magazine Electronics and Wireless World presents articles discussing logic circuits, for example, DIY PLD, in its June 1989 issue, Pp. 578-581 81.3 Registers and Their Applications B.R. Bannister and d.g. whitehead The basic building block of any register is the flip-flop, but, just as there are several types of flip-flop, there are many different register arrangements, and an idea of the vast range and their interrelationships is given in Fig. 81. 27 The simplest type of flip-flop is the set-reset flip-flop which can be constructed simply by cross-connecting two NAND/NOR gates. This forms an asynchronous flip-flop in which the set or reset signal determines both what the flip-flop is to do and when it is to operate. In fact, if a state change is required, the flip-flop begins to change state as soon as the input change is detected. This flip-flop is therefore useful as a latch which is used to detect when some event has occurred, and is often referred to as a flag since it indicates to other circuitry that the event has occurred and remains set until the controlling circuitry responds by resetting it. Flags are widely used in digital systems to indicate a change of state and all microprocessors have a set of flags which, among other things, are used in deciding whether a program branch should or should not be made. Thus the 8086 family of microprocessors [Intel, 1989], for example, has a group of nine flags--three control flags used to control particular modes of operation of the processor and six status flags indicating whether certain conditions have resulted from the most recent arithmetic or logical instruction: zero, carry, auxiliary carry, overflow, sign and parity. For convenience, although they all act independently, these flags are grouped together into what is known as the flag register or program status word register. Gated Registers The more conventional meaning of register applies to a collection of identical flip-flops which are activated as a set rather than individually. They are, in general, available as four-bit or eight-bit and are used in multiples of eight bits in most cases. It is the number of flip-flops in each register that determines the width of the data e 2000 by CRC Press LLC
© 2000 by CRC Press LLC Related Topic 79.2 Logic Gates (IC) References Advanced Micro Devices, PAL Device Data Book, Sunnyvale, Calif.: Advanced Micro Devices, Inc., 1988. ANSI/IEEE Std 91-1984,IEEE Standard Graphic Symbols for Logic Functions, New York: The Institute of Electrical and Electronics Engineers, 1984. ANSI/IEEE Std 991-1986, IEEE Standard for Logic Circuit Diagrams, New York: The Institute of Electrical and Electronics Engineers, 1986. K.J. Breeding, Digital Design Fundamentals, 2nd ed., Englewood Cliffs, N.J.: Prentice-Hall, 1992. F.J. Hill and G.R. Peterson, Introduction to Switching Theory & Logical Design, 3rd ed., New York: John Wiley, 1981. M.M. Mano, Digital Design, 2nd ed., Englewood Cliffs, N.J.: Prentice-Hall, 1991. E.J. McCluskey, Logic Design Principles, Englewood Cliffs, N.J.: Prentice-Hall, 1986. Minc, PLDesigner-XL, The Next Generation in Programmable Logic Synthesis, Version 3.5, User’s Guide, Colorado Springs: Minc, Incorporated, 1996. R.S. Sandige, Modern Digital Design, New York: McGraw-Hill, 1990. Further Information The monthly magazine IEEE Journal on Solid-State Circuits presents papers discussing logic circuits, for example, “Automating the Design of Asynchronous Sequential Logic Circuits,” in its March 1991 issue, pp. 364–370. The monthly magazine IEEE Transactions on Computers presents papers discussing logic circuits, for example, “Concurrent Logic Programming as a Hardware Descriptive Tool,” in its January 1990 issue, pp. 72–88. Also, the monthly magazine Electronics and Wireless World presents articles discussing logic circuits, for example, “DIY PLD,” in its June 1989 issue, pp. 578–581. 81.3 Registers and Their Applications B.R. Bannister and D.G. Whitehead The basic building block of any register is the flip-flop, but, just as there are several types of flip-flop, there are many different register arrangements, and an idea of the vast range and their interrelationships is given in Fig. 81.27. The simplest type of flip-flop is the set-reset flip-flop which can be constructed simply by cross-connecting two NAND/NOR gates. This forms an asynchronous flip-flop in which the set or reset signal determines both what the flip-flop is to do and when it is to operate. In fact, if a state change is required, the flip-flop begins to change state as soon as the input change is detected. This flip-flop is therefore useful as a latch which is used to detect when some event has occurred, and is often referred to as a flag since it indicates to other circuitry that the event has occurred and remains set until the controlling circuitry responds by resetting it. Flags are widely used in digital systems to indicate a change of state and all microprocessors have a set of flags which, among other things, are used in deciding whether a program branch should or should not be made. Thus the 8086 family of microprocessors [Intel, 1989], for example, has a group of nine flags—three control flags used to control particular modes of operation of the processor and six status flags indicating whether certain conditions have resulted from the most recent arithmetic or logical instruction: zero, carry, auxiliary carry, overflow, sign and parity. For convenience, although they all act independently, these flags are grouped together into what is known as the flag register or program status word register. Gated Registers The more conventional meaning of register applies to a collection of identical flip-flops which are activated as a set rather than individually. They are, in general, available as four-bit or eight-bit and are used in multiples of eight bits in most cases. It is the number of flip-flops in each register that determines the width of the data