9.1.4.5.1InterruptBanking21Ina multiprocessorimplementation,for PPls and SGls,GICcan havemultiple interrupts withthe same interrupt ID Itis identified uniquely by the combinationof its interrupt ID and itsassociatedCPUinterfaceSuchaninterruptiscalledabankedinterruptARMO82019-4-7
9.1.4.5.1 Interrupt Banking In a multiprocessor implementation, for PPIs and SGIs, GIC can have multiple interrupts with the same interrupt ID It is identified uniquely by the combination of its interrupt ID and its associated CPU interface Such an interrupt is called a banked interrupt ARM08 2019-4-7 21
9.1.4.5.2RegisterBanking22Register banking refers to implementing multiple copiesof a registerat the same address This occurs inMultiprocessorimplementationforsomeregistersthat are correspondingtobanked interruptsGlCthat implements security extensions toprovide separate secureandnonsecurecopiesofregistersARM082019-4-7
9.1.4.5.2 Register Banking Register banking refers to implementing multiple copies of a register at the same address This occurs in Multiprocessor implementation for some registers that are corresponding to banked interrupts GIC that implements security extensions to provide separate secure and nonsecure copies of registers ARM08 2019-4-7 22
9.2 Interrupt Sources23 9.2.1 Interrupt Sources 9.2.2 Interrupt TableARM082019-4-7
9.2 Interrupt Sources 9.2.1 Interrupt Sources 9.2.2 Interrupt Table ARM08 2019-4-7 23
9.2.1InterruptSources24 Interrupt sources pass through INT_COMBINER which combinesinterruptsourcesARMO82019-4-7
9.2.1 Interrupt Sources Interrupt sources pass through INT_COMBINER which combines interrupt sources ARM08 2019-4-7 24
ARMCore83uiu昌2GIC(PL390)101AXI IF forAXIIF forCPUIFDistri.Non-CombinedasInterruptCore SFRInterconnectionsAPBIFforINT_COMBINERNon-CombinedCombined Interrupt...Interrupt[31:0][127:32]INT COMBINER(INSTANCE1)Non-Combined25ARM082019-4-7InterruptFiqure9-1Interrupt Sources Connection
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