Edge and Level16Edge-triggered: is asserted on detection of a rising edge of an7interrupt signal Level-sensitive:is asserted whenever interrupt signal level is HIGH, anddissertedwheneverlevelisLOWARM082019-4-7
Edge and Level Edge-triggered: is asserted on detection of a rising edge of an interrupt signal Level-sensitive: is asserted whenever interrupt signal level is HIGH, and disserted whenever level is LOW ARM08 2019-4-7 16
1-N andN-NThere aretwomodelsforhandling interrupts: 1-N modelOnlyoneprocessorhandlesthisinterruptSystemdetermineswhichprocessorhandlesaninterrupt N-N modelAll processorsreceivetheinterruptindependentlyWhen a processoracknowledges the interrupt,the interrupt pending stateisclearedonlyforthatprocessor,andthe interruptremainspendingfor otherprocessorsARM082019-4-7
1-N and N-N ARM08 2019-4-7 17 There are two models for handling interrupts: 1-N model Only one processor handles this interrupt System determines which processor handles an interrupt N-N model All processors receive the interrupt independently When a processor acknowledges the interrupt, the interrupt pending state is cleared only for that processor, and the interrupt remains pending for other processors
9.1.4.3Spuriouslnterrupts18Spurious interruptistheoneno longerrequiredWhen processor acknowledgesinterrupt,GlCreturnsa special interruptIDforspuriousinterruptsThisoccursduetoChangeininterruptstate Software that has re-programmed GiC to change processing requirementsforinterruptInterruptthatis handling1-Nmodel andotherprocessorhasacknowledgedinterruptARM082019-4-7
9.1.4.3 Spurious Interrupts Spurious interrupt is the one no longer required When processor acknowledges interrupt, GIC returns a special interrupt ID for spurious interrupts This occurs due to Change in interrupt state Software that has re-programmed GIC to change processing requirements for interrupt Interrupt that is handling 1-N model and other processor has acknowledged interrupt ARM08 2019-4-7 18
9.1.4.4 Security States19Processorinnonsecure statecanmakeonlynonsecureaccessestoa Glc in secure state can make both secure and non-secure accesses to a GlCSoftwarein nonsecurestateisdescribed as Nonsecure softwareinsecurestateisdescribedassecuresoftwareARM082019-4-7
9.1.4.4 Security States Processor in nonsecure state can make only nonsecure accesses to a GIC in secure state can make both secure and non-secure accesses to a GIC Software in nonsecure state is described as Nonsecure software in secure state is described as secure software ARM08 2019-4-7 19
9.1.4.5InterruptBanking20 9.1.4.5.1 Interrupt Banking 9.1.4.5.2 Register BankingARM082019-4-7
9.1.4.5 Interrupt Banking 9.1.4.5.1 Interrupt Banking 9.1.4.5.2 Register Banking ARM08 2019-4-7 20