8259A intel. - CONTROL LOGIC CA50 CAS2- INTERNAL BUS 2314 Figure 4b.8259A Block Diagram 6
8259A 231468 –6 Figure 4b. 8259A Block Diagram 6
intel. 8259A THE CASCADE BUFFER/COMPARATOR dat hersdighr (CA 2)ar are inpt 彩/ 2的 inan system are the nINTA from the CPU group.the INTERRUPT SEQUENCE abity.Th ond Du tter allow e cPy. any g of the The events cur as follows inan MCS-0/8 sys was ng IRR bit(s) Both the heN9i8An88tppepmasandsnb PIC rec arted.fa higher between parts.The er should be aware of the 8259A 1
8259A THE CASCADE BUFFER/COMPARATOR This function block stores and compares the IDs of all 8259A’s used in the system. The associated three I/O pins (CAS0-2) are outputs when the 8259A is used as a master and are inputs when the 8259A is used as a slave. As a master, the 8259A sends the ID of the interrupting slave device onto the CAS0 –2 lines. The slave thus selected will send its preprogrammed subroutine address onto the Data Bus during the next one or two consecutive INTA pulses. (See section ‘‘Cascading the 8259A’’.) INTERRUPT SEQUENCE The powerful features of the 8259A in a microcomputer system are its programmability and the interrupt routine addressing capability. The latter allows direct or indirect jumping to the specific interrupt routine requested without any polling of the interrupting devices. The normal sequence of events during an interrupt depends on the type of CPU being used. The events occur as follows in an MCS-80/85 system: 1. One or more of the INTERRUPT REQUEST lines (IR7 –0) are raised high, setting the corresponding IRR bit(s). 2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate. 3. The CPU acknowledges the INT and responds with an INTA pulse. 4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set, and the corresponding IRR bit is reset. The 8259A will also release a CALL instruction code (11001101) onto the 8-bit Data Bus through its D7 –0 pins. 5. This CALL instruction will initiate two more INTA pulses to be sent to the 8259A from the CPU group. 6. These two INTA pulses allow the 8259A to release its preprogrammed subroutine address onto the Data Bus. The lower 8-bit address is released at the first INTA pulse and the higher 8-bit address is released at the second INTA pulse. 7. This completes the 3-byte CALL instruction released by the 8259A. In the AEOI mode the ISR bit is reset at the end of the third INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt sequence. The events occuring in an 8086 system are the same until step 4. 4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set and the corresponding IRR bit is reset. The 8259A does not drive the Data Bus during this cycle. 5. The 8086 will initiate a second INTA pulse. During this pulse, the 8259A releases an 8-bit pointer onto the Data Bus where it is read by the CPU. 6. This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the end of the second INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine. If no interrupt request is present at step 4 of either sequence (i.e., the request was too short in duration) the 8259A will issue an interrupt level 7. Both the vectoring bytes and the CAS lines will look like an interrupt level 7 was requested. When the 8259A PIC receives an interrupt, INT becomes active and an interrupt acknowledge cycle is started. If a higher priority interrupt occurs between the two INTA pulses, the INT line goes inactive immediately after the second INTA pulse. After an unspecified amount of time the INT line is activated again to signify the higher priority interrupt waiting for service. This inactive time is not specified and can vary between parts. The designer should be aware of this consideration when designing a system which uses the 8259A. It is recommended that proper asynchronous design techniques be followed. 7
8259A intel. REG CA52+ INTERNAL BUS 231468-7 Figure 4c.8259A Block Diagram INTERRUPT SEQUENCE OUTPUTS MCS-80,MCS-85 COR DOW NT STA CALL CODE 11001101 231488-8 Sys
8259A 231468 –7 Figure 4c. 8259A Block Diagram 231468 –8 Figure 5. 8259A Interface to Standard System Bus INTERRUPT SEQUENCE OUTPUTS MCS-80, MCS-85 This sequence is timed by three INTA pulses. During the first INTA pulse the CALL opcode is enabled onto the data bus. Content of First Interrupt Vector Byte D7 D6 D5 D4 D3 D2 D1 D0 CALL CODE 1 1 0 0 1 1 0 1 During the second INTA pulse the lower address of the appropriate service routine is enabled onto the data bus. When Interval e 4 bits A5–A7 are programmed, while A0–A4 are automatically inserted by the 8259A. When Interval e 8 only A6 and A7 are programmed, while A0–A5 are automatically inserted. 8