Encoding Registers P261 Fioure 44 Each register has 4-bit ID 各eax0 号esi6 ecx 1 号edi sedx ges geba ebp Same encoding as in IA32, but IA32 using only 3-bit ID Register ID 8 indicates"no register a Will use this in our hardware design in multiple places Processor
– 11 – Processor Encoding Registers Each register has 4-bit ID ◼ Same encoding as in IA32, but IA32 using only 3-bit ID Register ID 8 indicates “no register” ◼ Will use this in our hardware design in multiple places %eax %ecx %edx %ebx %esi %edi %esp %ebp 0 1 2 3 6 7 4 5 P261 Figure 4.4
Instruction Example P261 Flgure 43 Addition Instruction Generic Form Encoded Representation addi rA rB 60|rA a Add value in register ra to that in register rB Store result in register rB Note that Y86 only allows addition to be applied to register data Set condition codes based on result ■eg,add1号eax,号 esi Encoding:6006 a Two-byte encoding First indicates instruction type Second gives source and destination registers Processor
– 12 – Processor Instruction Example Addition Instruction ◼ Add value in register rA to that in register rB ⚫ Store result in register rB ⚫ Note that Y86 only allows addition to be applied to register data ◼ Set condition codes based on result ◼ e.g., addl %eax,%esi Encoding: 60 06 ◼ Two-byte encoding ⚫ First indicates instruction type ⚫ Second gives source and destination registers addl rA, rB 6 0 rA rB Encoded Representation Generic Form P261 Figure 4.3
Arithmetic and Logical Operations Instruction Code Function Code Add ■ Refer to generically as“op1” addl rA, rB 60|rA ■ Encodings differ only by “ function code Subtract (rA from rB) e LoW-order 4 bytes in first instruction word subl rA, rB rArB a Set condition codes as side effect And a Notice: no multiply or divide andI rA, rB 6|2A operation Exclusive-Or xor1 TA, rB rA -13 Processor
– 13 – Processor Arithmetic and Logical Operations ◼ Refer to generically as “OPl” ◼ Encodings differ only by “function code” ⚫ Low-order 4 bytes in first instruction word ◼ Set condition codes as side effect ◼ Notice: no multiply or divide operation addl rA, rB 6 0 rA rB subl rA, rB 6 1 rA rB andl rA, rB 6 2 rA rB xorl rA, rB 6 3 rA rB Add Subtract (rA from rB) And Exclusive-Or Instruction Code Function Code
Move Operations P259 Foure 42 rrmovlrA, rB 20|rA Register→> Register 308rB mmediate→> Register irmovlv rB rmmovlrA, D(rB)4 o rA rB D Register→> Memory mrmovlD(rB),TA 50 TArBD Memory→> Register a Like the la32 movl instruction a Simpler format for memory addresses a Give different names to keep them distinct 14- Distinct清楚的 Processor
– 14 – Processor Move Operations ◼ Like the IA32 movl instruction ◼ Simpler format for memory addresses ◼ Give different names to keep them distinct rrmovl rA, rB 2 0 rA rB Register --> Register Immediate --> Register irmovl V, rB 3 0 8 rB V Register --> Memory rmmovl rA, D(rB) 4 0 rA rB D Memory --> Register mrmovl D(rB), rA 5 0 rA rB D P259 Figure 4.2 Distinct: 清楚的
Move Instruction Examples A32 Y86 Encoding movl $Oxabcd edx irmovl $0xabcd, edx 3082cdab0000 movl esp, gebx rrmovl esp, ebx 2043 movl -12(ebp),ecx mrmovl-12(ebp),%ecx 50 15 f4 ffffff movl esi, 0x41c(esp) rmmovl esi, 0x41c(esp) 40 64 1c 04 0000 mov1$0 abcd,(号eax) mov1eax,12(号eax,.号edx) movl(ebp, eax, 4),ecx -15 Processor
– 15 – Processor Move Instruction Examples movl $0xabcd, %edx irmovl $0xabcd, %edx 30 82 cd ab 00 00 IA32 Y86 Encoding movl %esp, %ebx rrmovl %esp, %ebx 20 43 movl -12(%ebp),%ecx mrmovl -12(%ebp),%ecx 50 15 f4 ff ff ff movl %esi,0x41c(%esp) rmmovl %esi,0x41c(%esp) movl $0xabcd, (%eax) — movl %eax, 12(%eax,%edx) — movl (%ebp,%eax,4),%ecx — 40 64 1c 04 00 00