Reading DRAM supercell (2, 1) Step 2(a): Column access strobe(CAS) selects column 1 Step 2(b): Supercell (2, 1) copied from buffer to data lines, and eventually back to the U 16x8 DRAM chip cols 0 CAS =1 2 0 i rows memory controller supercell 2 (2,1) 8 data Figure 6.4 (b)P460 nternal row buffer
11 Reading DRAM supercell (2,1) • Step 2(a): Column access strobe (CAS) selects column 1. • Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU. supercell (2,1) cols rows 0 1 2 3 0 1 2 3 internal row buffer 16 x 8 DRAM chip CAS = 1 addr data 2 / 8 / memory controller Figure 6.4 (b) P460
Memory modules addr (row i,col= 3) 口: supercell(ij DRAM O 64 MB memory module consisting of DRAM 7 eight 8MX8 DRAMS dat bits bits bits bitsbits bits bits bits 56-63485540473239243116-238-150-7 63565548474039323124231615870 Memory controller 64-bit doubleword at main memory address a Figure 6.5 P461 64-bit doubleword to CPU chip 12
12 Memory modules : supercell (i,j) 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 64-bit doubleword at main memory address A addr (row = i, col = j) data 64 MB memory module consisting of eight 8Mx8 DRAMs Memory controller bits 0-7 DRAM 7 DRAM 0 bits 8-15 bits 16-23 bits 24-31 bits 32-39 bits 40-47 bits 48-55 bits 56-63 64-bit doubleword to CPU chip Figure 6.5 P461
Enhanced drams All enhanced DRaMs are built around the conventional dRaM core Fast page mode DRAM (FPM DRam) Access contents of row with [ras, CAs, CAS, Cas CAS] instead of [(Ras, CAS), (RAS, CAS (RAS, CAS), (RAS, CAS
13 Enhanced DRAMs • All enhanced DRAMs are built around the conventional DRAM core • Fast page mode DRAM (FPM DRAM) – Access contents of row with [RAS, CAS, CAS, CAS, CAS] instead of [(RAS,CAS), (RAS,CAS), (RAS,CAS), (RAS,CAS)]
Enhanced drams Extended data out DRAM (EDO DRAM Enhanced FPM DRAM with more closely spaced CAS signals. Synchronous DRAM(SDRAM) Driven with rising clock edge instead of asynchronous control signals
14 Enhanced DRAMs • Extended data out DRAM (EDO DRAM) – Enhanced FPM DRAM with more closely spaced CAS signals. • Synchronous DRAM (SDRAM) – Driven with rising clock edge instead of asynchronous control signals
Enhanced drams Double data-rate synchronous DRAM(DDR SDRAM) Enhancement of sdram that uses both clock edges as control signals Video RAM (VRaM) Like FPM DRAM, but output is produced by shifting row buffer Dual ported (allows concurrent reads and writes 15
15 Enhanced DRAMs • Double data-rate synchronous DRAM (DDR SDRAM) – Enhancement of SDRAM that uses both clock edges as control signals. • Video RAM (VRAM) – Like FPM DRAM, but output is produced by shifting row buffer – Dual ported (allows concurrent reads and writes)