6.1流水线乘法果加器设计6.1.2电路结构与工作原理2.调用加法器和锁存器ADDERODo you wantto pipeline the function?dataa[15.01clockresut[15..0]No上datab[15..0]OYes,I wantan outputlatencyofClock cyclescoutCreate an.asynchronous ClearinputCreate aClock Enable input图6-10为加法器增加流水线功能
6.1流水线乘法累加器设计 6.1.2 电路结构与工作原理 图6-10 为加法器增加流水线功能 2. 调用加法器和锁存器
6.1流水线乘法累加器设计6.1.2电路结构与工作原理福2.调用加法器和锁存器LPM_FFVersion6.0AboutDocumentation1Parameter2Simulation3SummarySettingsLibraryPageOptionalInputsGeneralHow many flipflops do youwant?REGODFFdata[7.0]Which type of flipflops do you want?>clockc[7.0]ODFflipflopTflipflopUse'data'input port (acts as a bitwise enableif no load signal ls used)Create a ClockEnable input图6-11为LPM寄存器选择D触发器类型
6.1流水线乘法累加器设计 6.1.2 电路结构与工作原理 图6-11 为LPM寄存器选择D触发器类型 2. 调用加法器和锁存器
6.1流水线乘法累加器设计6.1.3电路时序仿真与测试Flow StatusSuccessful -Thu AugQuartus II Version6.0 Bui1d20206/20MULTADDRevision NameMULTADDTop-level Entity HameFamilyCyelone IIDeviceEP2C8Q208C8FinalTiming ModelsYesMet timing requirements223/8,256(3%)Total logic elements127Total registersTotal pins34/138(25%)0Total virtual pins0/165,888（0%)Total memory bitsEmbedded Multiplier 9-bit elements0/36(0%)Total PLLs0/2(0%)图6-12基于逻辑宏单元的设计报告
6.1流水线乘法累加器设计 6.1.3 电路时序仿真与测试 图6-12 基于逻辑宏单元的设计报告