《数字系统与VHDL程序设计语言》课程教学资源（PPT课件讲稿，共六章）

常用数字电路回顾 (1)编码器 A7 A6 A5 8X3 Y2 输出 输入 A4 Y1 信号 信号 A3 A2 编码器 A1 AO EN—>使能端口O

常用数字电路回顾 （1）编码器 A7 A6 A5 A4 A3 A2 A1 A0 EN Y2 Y1 Y0 8 X 3 编 码  器 输入 信号  输出 信号 使能端口

A5 A4 A3 A2 A1 A0 Y2 Y1 YO 00 000 0000000 0000 000000 00000 00 00000 000000 0000 000 00000 U000 00 注:EN为1时编码器工作

注：EN为1时编码器工作 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 A7 A6 A5 A4 A3 A2 A1 A0 Y 2 Y1 Y0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 A7 A6 A5 A4 A3 A2 A1 A0 Y 2 Y1 Y0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 A7 A6 A5 A4 A3 A2 A1 A0 Y 2 Y1 Y0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 A7 A6 A5 A4 A3 A2 A1 A0 Y 2 Y1 Y0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 A7 A6 A5 A4 A3 A2 A1 A0 Y 2 Y1 Y0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 A7 A6 A5 A4 A3 A2 A1 A0 Y 2 Y1 Y0

Electro alysis置 indow Hell 口副当略囚团? 举例半 5 6 GS 3 2 A1 74148 参看EWB辅助电路

举例 参看EWB辅助电路

(2)译码器 Y3 Y2 Y1 YO AI A0 1110 0 1011 0111 0011 010 Vcc YO Y1 Y2 Y3 Y4 Y5 Y6 6151413121110 译码器 S A AO Y3Y2 Y YO 000 011 A0 A1 A2 S3 S2 S1 Y7 GND cT74138

（2）译码器 Y3 Y2 Y1 Y0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 A1 A0 0 0 0 1 1 0 1 1 A1 A0 0 0 0 1 1 0 1 1 Y3 Y2 Y1 Y0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 S 1 × × 1 1 1 1 0 0 0 0 译码器 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Vcc Y0 Y1 Y2 Y3 Y4 Y5 Y6 A0 A1 A2 S3 S2 S1 Y7 GND CT74138

POWER cc-310 OUTPUT ON CPLD/FPGA Development System OOFF 智熊型可编程数字开发家统 DC 7. 5V aloo (-) As AgAr