Further information Data books and Device Index: D. M. Howell, Ed IC Master, Garden City, NY: Hearst Business Communications, annual Engineering Staff, Advanced BiCMOS Technology Data Book, Dallas: Texas Instruments, 1994 Engineering Staff, Advanced High-Speed CMOS Logic Data Book, Dallas: Texas Instruments, 1996 Engineering Staff, ALS/AS Logic Data Book, Dallas: Texas Instruments, 1995 Engineering Staff, ECLinPS Data, Phoenix: Motorola, 1995 Engineering Staff, FACT Advanced CMOS Logic Databook, Santa Clara, Calif: National Semiconductor Corporation, 1993 Engineering Staff, FACT Data, Phoenix: Motorola, 1996 Engineering Staff, FACT &- LS TTL Data, Phoenix: Motorola, 19 Engineering Staff, Low-Voltage Logic Data Book, Dallas: Texas Instruments, 1996 Engineering Staff, MECL Data, Phoenix: Motorola, 1993 Journals and Trade Magazines EDN, Highlights Ranch, Colo. Cahners Publishing Electronic Design, Cleveland, Ohio: Penton Publishing. Electronic Engineering Times, Manhasset, N Y. CMP Publications. IEEE Journal of Solid-State Circuits, New York: Institute of Electrical and Electronic Engineers. IEEE Transactions on Circuits and Systems, Part I Fundamental Theory and Applications, New York: Institute f Electrical and Electronic Engineers Internet Addresses for Digital Device Data Sheets Motorola. Inc http://desIgn-net.com National Semiconductor Corp http://www.national.com/design/index.html Texas Instruments, Inc. http://www.ti.com/sc/docs/schome.htm 79.2 Logic Gates(IC) Peter graham This section introduces and analyzes the electronic circuit realizations of the basic gates of the three technologies: transistor-transistor logic(TTL), emitter-coupled logic(ECL, and complementary metal-oxide semiconductor (CMOS)logic. These circuits are commercially available on small-scale integration chips and are also the building blocks for more elaborate logic systems. The three technologies are compared with regard to speed, power consumption, and noise immunity, and parameters are defined which facilitate these comparisons. also included are recommendations which are useful in choosing and using these technologies. Gate Specification Parameters Theoretically almost any logic device or system could be constructed by wiring together the appropriate figuration of the basic gates of the selected technology. In practice, however, the gates are interconnected during the fabrication process to produce a desired system on a single chip. The circuit complexity of a given hip is described by one llowing four rather broad classifications: Small-Scale Integration(SSI). The inputs and outputs of every gate are available for external connection at the chip pins(with the exception that exclusive OR and AND-OR gates are considered SSI) Medium-Scale Integration(MSI). Several gates are interconnected to perform somewhat more elaborate logic functions such as flip-flops, counters, multiplexers, etc Based on P. Graham, "Gates, " in Handbook of Modern Electronics and Electrical Engineering, C. Belove, Ed, New York: wiley-Interscience, 1986, Pp. 864-876. With permission e 2000 by CRC Press LLC
© 2000 by CRC Press LLC Further Information Data Books and Device Index: D. M. Howell, Ed. IC Master, Garden City, NY: Hearst Business Communications, annual. Engineering Staff, Advanced BiCMOS Technology Data Book, Dallas: Texas Instruments, 1994. Engineering Staff, Advanced High-Speed CMOS Logic Data Book, Dallas: Texas Instruments, 1996. Engineering Staff, ALS/AS Logic Data Book, Dallas: Texas Instruments, 1995. Engineering Staff, ECLinPS Data, Phoenix: Motorola, 1995. Engineering Staff, FACT Advanced CMOS Logic Databook, Santa Clara, Calif: National Semiconductor Corporation, 1993. Engineering Staff, FACT Data, Phoenix: Motorola, 1996. Engineering Staff, FACT & LS TTL Data, Phoenix: Motorola, 1992. Engineering Staff, Low-Voltage Logic Data Book, Dallas: Texas Instruments, 1996. Engineering Staff, MECL Data, Phoenix: Motorola, 1993. Journals and Trade Magazines: EDN, Highlights Ranch, Colo.: Cahners Publishing. Electronic Design, Cleveland, Ohio: Penton Publishing. Electronic Engineering Times, Manhasset, N.Y.: CMP Publications. IEEE Journal of Solid-State Circuits, New York: Institute of Electrical and Electronic Engineers. IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and Applications, New York: Institute of Electrical and Electronic Engineers. Internet Addresses for Digital Device Data Sheets: Motorola, Inc. http://Design-net.com National Semiconductor Corp. http://www.national.com/design/index.html Texas Instruments, Inc. http://www.ti.com/sc/docs/schome.htm 79.2 Logic Gates (IC)1 Peter Graham This section introduces and analyzes the electronic circuit realizations of the basic gates of the three technologies: transistor-transistor logic (TTL), emitter-coupled logic (ECL), and complementary metal-oxide semiconductor (CMOS) logic. These circuits are commercially available on small-scale integration chips and are also the building blocks for more elaborate logic systems. The three technologies are compared with regard to speed, power consumption, and noise immunity, and parameters are defined which facilitate these comparisons. Also included are recommendations which are useful in choosing and using these technologies. Gate Specification Parameters Theoretically almost any logic device or system could be constructed by wiring together the appropriate configuration of the basic gates of the selected technology. In practice, however, the gates are interconnected during the fabrication process to produce a desired system on a single chip. The circuit complexity of a given chip is described by one of the following four rather broad classifications: • Small-Scale Integration (SSI). The inputs and outputs of every gate are available for external connection at the chip pins (with the exception that exclusive OR and AND-OR gates are considered SSI). • Medium-Scale Integration (MSI). Several gates are interconnected to perform somewhat more elaborate logic functions such as flip-flops, counters, multiplexers, etc. 1 Based on P. Graham, “Gates,” in Handbook of Modern Electronics and Electrical Engineering, C. Belove, Ed., New York: Wiley-Interscience, 1986, pp. 864–876. With permission
tr FIGURE 79.7 Definitions of switching times. Large-Scale Integration(LSI). Several of the more elaborate circuits associated with MSI are intercon- nected within the integrated circuit to form a logic system on a single chip Chips such as calculators, digital clocks, and small microprocessors are examples of LSI. Very-Large-Scale Integration(VISI). This designation is usually reserved for chips having a very high density, 1000 or more gates per chip. These include the large single-chip memories, gate arrays, and Specifications of logic speed require definitions of switching times. These definitions can be found in the introductory pages of most data manuals. Four of them pertain directly to gate circuits. These are(see also Fig.797) LOw-to-HIGH Propagation Delay Time(tpLH). The time between specified reference points on the put and output voltage waveforms when the output is changing from low to high HIGH-to-LOW Propagation Delay Tune(tPHL. The time between specified reference points on the input and output voltage waveforms when the output is changing from high to low Propagation Delay Time(tpp). The average of the two propagation delay times: tPD=(tpD+ tpHL)/2. LOW-to-HIGH Transition Time(tTLH). The rise time between specified reference points on the LOW-to HIGH shift of the output waveform HIGH-to-LOW Transition Time(tTHL). The fall time between specified reference points on the HIGH-to- LOW shift of the output waveform. The reference points usually are 10 and 90% of the voltage level difference Power consumption, driving capability, and effective loading of gates are defined in terms of currents. Supply Current, Outputs High(LxH). The current delivered to the chip by the power supply when all outputs are open and at the logical 1 level. The xx subscript depends on the technology pply Current, Outputs Low(Id). The current delivered to the chip by the supply when all outputs are open and at the logical 0 level. Supply Current, Worst Case(Ix). When the output level is unspecified, the input conditions are assumed to correspond to maximum supply current c2000 by CRC Press LLC
© 2000 by CRC Press LLC • Large-Scale Integration (LSI). Several of the more elaborate circuits associated with MSI are interconnected within the integrated circuit to form a logic system on a single chip. Chips such as calculators, digital clocks, and small microprocessors are examples of LSI. • Very-Large-Scale Integration (VLSI). This designation is usually reserved for chips having a very high density, 1000 or more gates per chip. These include the large single-chip memories, gate arrays, and microcomputers. Specifications of logic speed require definitions of switching times. These definitions can be found in the introductory pages of most data manuals. Four of them pertain directly to gate circuits. These are (see also Fig. 79.7): • LOW-to-HIGH Propagation Delay Time (tPLH). The time between specified reference points on the input and output voltage waveforms when the output is changing from low to high. • HIGH-to-LOW Propagation Delay Tune (tPHL). The time between specified reference points on the input and output voltage waveforms when the output is changing from high to low. • Propagation Delay Time (tPD). The average of the two propagation delay times: tPD = (tPD + tPHL) /2. • LOW-to-HIGH Transition Time (tTLH). The rise time between specified reference points on the LOW-toHIGH shift of the output waveform. • HIGH-to-LOW Transition Time (tTHL). The fall time between specified reference points on the HIGH-toLOW shift of the output waveform. The reference points usually are 10 and 90% of the voltage level difference in each case. Power consumption, driving capability, and effective loading of gates are defined in terms of currents. • Supply Current, Outputs High (IxxH). The current delivered to the chip by the power supply when all outputs are open and at the logical 1 level. The xx subscript depends on the technology. • Supply Current, Outputs Low (IxxL). The current delivered to the chip by the supply when all outputs are open and at the logical 0 level. • Supply Current,Worst Case (Ixx).When the output level is unspecified, the input conditions are assumed to correspond to maximum supply current. FIGURE 79.7 Definitions of switching times
Input HIGH Current(IH). The current flowing into an input when the specified HIGH voltage is applied Input LOW Current(Iv. The current flowing into an input when the specified LOW voltage is applied Output HIGH Current(IoH). The current flowing into the output when it is in the HIGH state. IoHmax is the largest IoH for which VoH 2 VoHmin is guaranteed. Output LOW Current(Iow). The current flowing into the output when it is in the LOW state. I the largest Iot for which Vor 2 VoLmax is guaranteed. The most important voltage definitions are concerned with establishing ranges on the logical 1(HIGH)and Minimum High-Level Input Voltage(VIHmin). The least positive value of input voltage guaranteed result in the output voltage level specified for a logical 1 input maximum Low-Level Input Voltage(ViLmax). The most positive value of input voltage guaranteed to esult in the output voltage level specified for a logical 0 input. Minimum High-Level Output Voltage(VoHmin). The guaranteed least positive output voltage when the input is properly driven to produce a logical 1 at the output Maximum Low-Level Output Voltage(VoLmax). The guaranteed most positive output voltage when the input is properly driven to produce a logical 0 at the output Noise Margins. NMH= VOHmin-VIHmin is how much larger the guaranteed least positive output logical I level is than the least positive input level that will be interpreted as a logical 1. It represents how large a negative-going glitch on an input 1 can be before it affects the output of the driven device. Similarly, NM.=VItmax-VoLma is the amplitude of the largest positive-going glitch on an input 0 that will not affect the output of the driven device. Finally, three important definitions are associated with specifying the load that can be driven by a gate. Since in most cases the load on a gate output will be the sum of inputs of other gates, the first definition characterizes the relative current requirements of gate inputs. Load Factor(LF). Each logic family has a reference gate, each of whose inputs is defined to be a unit load in both the HIGH and the LOW conditions. The respective ratios of the input currents IH and IL of a given input to the corresponding IH and In of the reference gate define the HIGH and LOW load factors of that input. Drive Factor(DF). A device output has drive factors for both the HIGH and the LOw output conditions. These factors are defined as the respective ratios of JoHmax and LoMax of the gate to IoHmax and IoLmar of the reference gate Fan-Out. For a given gate the fan-out is defined as the maximum number of inputs of the same type of gate that can be properly driven by that gate output. When gates of different load and drive factors are interconnected, fan-out must be adjusted accordingly Bipolar Transistor Gates A logic circuit using bipolar junction transistors(B]Ts)can be classified either as saturated or as nonsaturated logic. A saturated logic circuit contains at least one BJT that is saturated in one of the stable modes of the circuit. In nonsaturated logic circuits none of the transistors is allowed to saturate. Since bringing a BJT out of saturation requires a few additional nanoseconds(called the storage time), nonsaturated logic is faster. The fastest circuits available at this time are emitter-coupled logic (ECL), with transistor-transistor logic (TtL having Schottky diodes connected to prevent the transistors from saturating( Schottky TTL) being a fairly close second. Both of these families are nonsaturated logic. All TTL families other than Schottky are saturated logic Transistor-Transistor logic TTL evolved from resistor-transistor logic(RTL) through the intermediate step of diode-transistor logic (dTl All three families are catalogued in data books published in 1968, but of the three only Ttl is still available e 2000 by CRC Press LLC
© 2000 by CRC Press LLC • Input HIGH Current (IIH). The current flowing into an input when the specified HIGH voltage is applied. • Input LOW Current (IIL). The current flowing into an input when the specified LOW voltage is applied. • Output HIGH Current (IOH). The current flowing into the output when it is in the HIGH state. IOHmax is the largest IOH for which VOH ³ VOHmin is guaranteed. • Output LOW Current (IOL). The current flowing into the output when it is in the LOW state. IOLmax is the largest IOL for which VOL ³ VOLmax is guaranteed. The most important voltage definitions are concerned with establishing ranges on the logical 1 (HIGH) and logical 0 (LOW) voltage levels. • Minimum High-Level Input Voltage (VIHmin). The least positive value of input voltage guaranteed to result in the output voltage level specified for a logical 1 input. • Maximum Low-Level Input Voltage (VILmax). The most positive value of input voltage guaranteed to result in the output voltage level specified for a logical 0 input. • Minimum High-Level Output Voltage (VOHmin). The guaranteed least positive output voltage when the input is properly driven to produce a logical 1 at the output. • Maximum Low-Level Output Voltage (VOLmax). The guaranteed most positive output voltage when the input is properly driven to produce a logical 0 at the output. • Noise Margins. NMH = VOHmin – VIHmin is how much larger the guaranteed least positive output logical 1 level is than the least positive input level that will be interpreted as a logical 1. It represents how large a negative-going glitch on an input 1 can be before it affects the output of the driven device. Similarly, NML = VILmax – VOLmax is the amplitude of the largest positive- going glitch on an input 0 that will not affect the output of the driven device. Finally, three important definitions are associated with specifying the load that can be driven by a gate. Since in most cases the load on a gate output will be the sum of inputs of other gates, the first definition characterizes the relative current requirements of gate inputs. • Load Factor (LF). Each logic family has a reference gate, each of whose inputs is defined to be a unit load in both the HIGH and the LOW conditions. The respective ratios of the input currents IIH and IIL of a given input to the corresponding IIH and IIL of the reference gate define the HIGH and LOW load factors of that input. • Drive Factor (DF). A device output has drive factors for both the HIGH and the LOW output conditions. These factors are defined as the respective ratios of IOHmax and IOLmax of the gate to IOHmax and IOLmax of the reference gate. • Fan-Out. For a given gate the fan-out is defined as the maximum number of inputs of the same type of gate that can be properly driven by that gate output. When gates of different load and drive factors are interconnected, fan-out must be adjusted accordingly. Bipolar Transistor Gates A logic circuit using bipolar junction transistors (BJTs) can be classified either as saturated or as nonsaturated logic. A saturated logic circuit contains at least one BJT that is saturated in one of the stable modes of the circuit. In nonsaturated logic circuits none of the transistors is allowed to saturate. Since bringing a BJT out of saturation requires a few additional nanoseconds (called the storage time), nonsaturated logic is faster. The fastest circuits available at this time are emitter-coupled logic (ECL), with transistor-transistor logic (TTL) having Schottky diodes connected to prevent the transistors from saturating (Schottky TTL) being a fairly close second. Both of these families are nonsaturated logic. All TTL families other than Schottky are saturated logic. Transistor-Transistor Logic TTL evolved from resistor-transistor logic (RTL) through the intermediate step of diode-transistor logic (DTL). All three families are catalogued in data books published in 1968, but of the three only TTL is still available