Q2 FIGURE 79.2 CMOS inverter circuit block diagram and operation. Q2 transistors FIGURE 79.3 CMOS two-input NAND circuit block diagram and operation. ECL Logic Family ECL is a higher-speed logic family. While it does not offer as large a variety of IC chips as are available in the TTL family, it is quite popular for logic applications requiring high-speed switching The active switching element used in the ECL family circuits is also the npn BJT. Unlike the TTl family, however, which switches the transistors into saturation when turning them on, ECL switching is designed to revent driving the transistors into saturation. Whenever bipolar transistors are driven into saturation, their witching speed will be limited by the charge carrier storage delay, a transistor operational characteristic. Thus, the switching speed of ECL circuits will be significantly higher than for TTL circuits. ECL operation is based c2000 by CRC Press LLC
© 2000 by CRC Press LLC ECL Logic Family ECL is a higher-speed logic family. While it does not offer as large a variety of IC chips as are available in the TTL family, it is quite popular for logic applications requiring high-speed switching. The active switching element used in the ECL family circuits is also the npn BJT. Unlike the TTL family, however, which switches the transistors into saturation when turning them on, ECL switching is designed to prevent driving the transistors into saturation. Whenever bipolar transistors are driven into saturation, their switching speed will be limited by the charge carrier storage delay, a transistor operational characteristic. Thus, the switching speed of ECL circuits will be significantly higher than for TTL circuits. ECL operation is based FIGURE 79.2 CMOS inverter circuit block diagram and operation. FIGURE 79.3 CMOS two-input NAND circuit block diagram and operation
ogio g OH(min) VIH(min Disallow- Indeter- Logic C O FIGURE 79.4 Switching device logic levels TABLE 79. 3 ignal Voltage Parameters for Selected Logic Subfamilies(in 2.0 0.5 74ASxX 0.4 2.0 74FXX 74HCxx 0.1 74HCTxX 0.1 2.0 8888983 74ACxx 0.4 74ACTxx 0.4 74AHCxx 0.1 3.85 74AHCTX 3.65 0.96 1.65 1.105 1.475 10Hxx 148 on switching a fixed amount of bias current that is less than the saturation amount between two different transistors. The basic circuit found in the ECl family is the differential amplifier. One side of the differential amplifier is controlled by a bias circuit and the other is controlled by the logic inputs to the gate. This logic family is also referred to as current-mode logic( CML) because of its current switching operation Logic Family Circuit Parameters Digital circuits and systems operate with only two states, logic I and 0, usually represented by two different voltage levels, a high and a low. The two logic levels actually consist of a range of values with the numerical quantities dependent upon the specific family that is used. Minimum high logic levels and maximum low logic levels are established by specifications for each family. Minimum device output levels for a logic high are called VOH(min) and minimum input levels are called VIH(min). The abbreviations for maximum output and input low logic levels are VoLmax) and VIL(max), respectively. Figure 79.4 shows the relationships between these parameters Logic voltage level parameters are illustrated for selected prominent logic subfamilies in Table 79.3. As seen in this illustration, there are many operational incompatibilities between major logic family types. Noise margin is a quantitative measure of a device's noise immunity. High-level noise margin( VNH)and low-level noise margin( VNL)are defined in Eqs. (79.1)and(79.2). e 2000 by CRC Press LLC
© 2000 by CRC Press LLC on switching a fixed amount of bias current that is less than the saturation amount between two different transistors. The basic circuit found in the ECL family is the differential amplifier. One side of the differential amplifier is controlled by a bias circuit and the other is controlled by the logic inputs to the gate. This logic family is also referred to as current-mode logic (CML) because of its current switching operation. Logic Family Circuit Parameters Digital circuits and systems operate with only two states, logic 1 and 0, usually represented by two different voltage levels, a high and a low. The two logic levels actually consist of a range of values with the numerical quantities dependent upon the specific family that is used. Minimum high logic levels and maximum low logic levels are established by specifications for each family. Minimum device output levels for a logic high are called VOH(min) and minimum input levels are called VIH(min). The abbreviations for maximum output and input low logic levels are VOL(max) and VIL(max), respectively. Figure 79.4 shows the relationships between these parameters. Logic voltage level parameters are illustrated for selected prominent logic subfamilies in Table 79.3. As seen in this illustration, there are many operational incompatibilities between major logic family types. Noise margin is a quantitative measure of a device’s noise immunity. High-level noise margin (VNH) and low-level noise margin (VNL) are defined in Eqs. (79.1) and (79.2). FIGURE 79.4 Switching device logic levels. TABLE 79.3 Logic Signal Voltage Parameters for Selected Logic Subfamilies (in Volts) Subfamily VOH(min) VOL(max) VIH(min) VIL(max) 74xx 2.4 0.4 2.0 0.8 74LSxx 2.7 0.5 2.0 0.8 74ASxx 2.5 0.5 2.0 0.8 74ALSxx 2.5 0.4 2.0 0.8 74Fxx 2.5 0.5 2.0 0.8 74HCxx 4.9 0.1 3.15 0.9 74HCTxx 4.9 0.1 2.0 0.8 74ACxx 3.8 0.4 3.15 1.35 74ACTxx 3.8 0.4 2.0 0.8 74AHCxx 4.5 0.1 3.85 1.65 74AHCTxx 3.65 0.1 2.0 0.8 10xxx –0.96 –1.65 –1.105 –1.475 10Hxxx –0.98 –1.63 –1.13 –1.48
DRIVEN GATE萨 IIH DRIVI DRIVEN GATE HIGH GATE萨2 curre 工H GATE F1 L DRIVEN GATE GATE F2 current ng DRIVEN GATE F FIGURE 79.5 Current loading of driving gates. TABLE 79.4 Worst Case Current Parameters for Selected Logic Subfamilies ubfamil 16 mA AA叭 8 mA 201 8 mA 20uA-100μ 201 0.6mA 74HCxx 4 mA 4AHCXX 74AHCTxX -50 mA -265μA500 10Hxxx 50 mA OH(min)vIH(min) (79.1) (79.2) Using the logic voltage values given in Table 79.3 for the selected subfamilies reveals that highest noise immunity is obtained with logic devices in the CMOS family, while lowest noise immunity is endemic to the ECL family. Switching circuit outputs are loaded by the inputs of the devices that they are driving, as illustrated in Fig. 79.5. Worst case input loading current levels and output driving current capabilities are listed in Table 79.4 for various logic subfamilies. The fan-out of a driving device is the ratio between its output current capabilities at each logic level and the corresponding gate input current loading value. Switching circuits based on bipolar transistors have fan-out limited primarily by the current-sinking and current-sourcing capabilities of the driving c2000 by CRC Press LLC
© 2000 by CRC Press LLC VNH = VOH(min) – VIH(min) (79.1) VNL = VIL(max) – VOL(max) (79.2) Using the logic voltage values given in Table 79.3 for the selected subfamilies reveals that highest noise immunity is obtained with logic devices in the CMOS family, while lowest noise immunity is endemic to the ECL family. Switching circuit outputs are loaded by the inputs of the devices that they are driving, as illustrated in Fig. 79.5. Worst case input loading current levels and output driving current capabilities are listed in Table 79.4 for various logic subfamilies. The fan-out of a driving device is the ratio between its output current capabilities at each logic level and the corresponding gate input current loading value. Switching circuits based on bipolar transistors have fan-out limited primarily by the current-sinking and current-sourcing capabilities of the driving device. FIGURE 79.5 Current loading of driving gates. TABLE 79.4 Worst Case Current Parameters for Selected Logic Subfamilies Subfamily IOH(max) IOL(max) IIH(max) IIL(max) 74xx –400 mA 16 mA 40 mA –1.6 mA 74LSxx –400 mA 8 mA 20 mA –400 mA 74ASxx –2 mA 20 mA 200 mA –2 mA 74ALSxx –400 mA 8 mA 20 mA –100 mA 74Fxx –1 mA 20 mA 20 mA –0.6 mA 74HCxx –4 mA 4 mA 1 mA –1 mA 74HCTxx –4 mA 4 mA 1 mA –1 mA 74ACxx –24 mA 24 mA 1 mA –1 mA 74ACTxx –24 mA 24 mA 1 mA –1 mA 74AHCxx –8 mA 8 mA 1 mA –1 mA 74AHCTxx –8 mA 8 mA 1 mA –1 mA 10xxx 50 mA –50 mA –265 mA 500 nA 10Hxxx 50 mA –50 mA –265 mA 500 nA
TABLE 79.5 Speed-Power Comparison for Selected Logic Subfamilies Static Power Delay Time, Dissipation, Speed-Power p 74x 10 777 74HCTXX 42×10-3 74ACx 0.010 0×10-3 74ACTxx 0.010 0×10-3 74AHCxX 25 10HxXx CMOS switching circuits are limited by the charging and discharging times associated with the output resistance of the driving gate and the input capacitance of the load gates. Thus, CMOS fan-out depends on the frequency of switching. With fewer(capacitive)loading inputs to drive, the maximum switching frequency of cMos devices will increase The switching speed of logic devices is dependent on the device's propagation delay time. The propagation delay of a logic device limits the frequency at which it can be operated. There are two propagation delay times specified for logic gates: tpHL, delay time for the output to change from high to low, and tPLH, delay time for the output to change from low to high. Average typical propagation delay times for a single gate are listed for several logic subfamilies in Table 79.5. The ECL family has the fastest switching speed. The amount of power required by an IC is normally specified in terms of the amount of current Icc (TTL family), IpD(CMOS family), or IEE(ECL family) drawn from the power supply For complex IC devices, the quired supply current is given under specified test conditions For Ttl chips containing simple gates, the average power dissipation Pp(ave) is normally calculated from two measurements, IccH(when all gate outputs high)and Icc (when all gate outputs are low). Table 79.5 compares the static power dissipation of several logic subfamilies. The ECL family has the highest power dissipation, while the lowest is attained with the CMOS family. It should be noted that power dissipation for the CMOS family is directly proportional to the gate input ignal frequency. For example, one would typically find that the power dissipation for a CMOS logic circuit would increase by a factor of 100 if the input signal frequency is increased from 1 kHz to 100 kHz The speed-power product is a relative figure of merit that is calculated by the formula given in Eq. (79. 3) This performance measurement is normally expressed in picojoules(pD) Speed-power product =(tPHL tPLH )/2 X Pp(ave) (79.3) A low value of speed-power product is desirable to implement high-speed(and, therefore, low propagation lelay time) switching devices that consume low amounts of power. Because of the nature of transistor switching circuits, it is difficult to attain high-speed switching with low power dissipation. The continued development f new IC logic families and subfamilies is largely due to the trade-offs between these two device switching parameters. The speed-power product for various subfamilies is also compared in Table 79.5. Interfacing Between Logic Families The interconnection of logic chips requires that input and output specifications be satisfied. Figure 79.6 illus- trates voltage and current requirements. The driving chips VOH(min) must be greater than the driven circuit VIH(minl, and the driver's VOLimax) must be less than VIL(max) for the loading circuit. Voltage level shifters must be e 2000 by CRC Press LLC
© 2000 by CRC Press LLC CMOS switching circuits are limited by the charging and discharging times associated with the output resistance of the driving gate and the input capacitance of the load gates. Thus, CMOS fan-out depends on the frequency of switching. With fewer (capacitive) loading inputs to drive, the maximum switching frequency of CMOS devices will increase. The switching speed of logic devices is dependent on the device’s propagation delay time. The propagation delay of a logic device limits the frequency at which it can be operated. There are two propagation delay times specified for logic gates: tPHL, delay time for the output to change from high to low, and tPLH, delay time for the output to change from low to high. Average typical propagation delay times for a single gate are listed for several logic subfamilies in Table 79.5. The ECL family has the fastest switching speed. The amount of power required by an IC is normally specified in terms of the amount of current ICC (TTL family), IDD (CMOS family), or IEE (ECL family) drawn from the power supply. For complex IC devices, the required supply current is given under specified test conditions. For TTL chips containing simple gates, the average power dissipation PD(ave) is normally calculated from two measurements, ICCH (when all gate outputs are high) and ICCL (when all gate outputs are low). Table 79.5 compares the static power dissipation of several logic subfamilies. The ECL family has the highest power dissipation, while the lowest is attained with the CMOS family. It should be noted that power dissipation for the CMOS family is directly proportional to the gate input signal frequency. For example, one would typically find that the power dissipation for a CMOS logic circuit would increase by a factor of 100 if the input signal frequency is increased from 1 kHz to 100 kHz. The speed-power product is a relative figure of merit that is calculated by the formula given in Eq. (79.3). This performance measurement is normally expressed in picojoules (pJ). Speed-power product = (tPHL + tPLH)/2 ¥ PD(ave) (79.3) A low value of speed-power product is desirable to implement high-speed (and, therefore, low propagation delay time) switching devices that consume low amounts of power. Because of the nature of transistor switching circuits, it is difficult to attain high-speed switching with low power dissipation. The continued development of new IC logic families and subfamilies is largely due to the trade-offs between these two device switching parameters. The speed-power product for various subfamilies is also compared in Table 79.5. Interfacing Between Logic Families The interconnection of logic chips requires that input and output specifications be satisfied. Figure 79.6 illustrates voltage and current requirements. The driving chip’s VOH(min) must be greater than the driven circuit’s VIH(min), and the driver’s VOL(max) must be less than VIL(max) for the loading circuit. Voltage level shifters must be TABLE 79.5 Speed-Power Comparison for Selected Logic Subfamilies Propagation Static Power Delay Time, Dissipation, Speed-Power Subfamily ns (ave.) mW (per gate) Product, pJ 74xx 10 10 100 74LSxx 9.5 2 19 74ASxx 1.5 2 13 74ALSxx 4 1.2 5 74Fxx 3 6 18 74HCxx 8 0.003 24 ¥ 10–3 74HCTxx 14 0.003 42 ¥ 10–3 74ACxx 5 0.010 50 ¥ 10–3 74ACTxx 5 0.010 50 ¥ 10–3 74AHCxx 5.5 0.003 16 ¥ 10–3 74AHCTxx 5 0.003 14 ¥ 10–3 10xxx 2 25 50 10Hxxx 1 25 25
DRIVING ro>工 DRIVEN CIRCUIT FIGURE 79.6 Circuit interfacing requirements. used to interface the circuits together if these voltage requirements are not met. Of course, a driving circuit's output must not exceed the maximum and minimum allowable input voltages for the driven circuit. Also, the current sinking and sourcing ability of the driver circuit's output must be greater than the total current requirements for the loading circuit Buffer gates or stages must be used if current requirements are not satisfied. All chips within a single logic family are designed to be compatible with other chips in the same family. Mixing chips from multiple subfamilies together within a single digital circuit can have adverse effects on the overall circuit's switching speed and noise immunity. Defining Terms Fan-out: The specification used to identify the limit to the number of loading inputs that can be reliably driven by a driving device's output Logic level: The high or low value of a voltage variable that is assigned to be a l or a 0 state. Noise immunity: A logic device s ability to tolerate input voltage fluctuation caused by noise without changing Its output state. Propagation delay time: The time delay from when the input logic level to a device is changed until the resultant output change is produced by that device. Speed-power product: An overall performance measurement that is used to compare the various logic families and subfamilies Truth table: A listing of the relationship of a circuits output that is produced for various combinations of logic levels at the inputs Related Topic 25.3 Application-Specific Integrated Circuits References A P Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Boston: Kluwer Academic, 1995 D.J. Comer, Digital Logic and State Machine Design, 2nd ed, Philadelphia: Saunders College Publishing, 1990 S. H. K. Embabi, A. Bellaouar, and M. I. Elmasry, Digital BiCMOS Integrated Circuit Design, Boston: Kluwer Academic, 1993 T. L. Floyd, Digital Fundamentals, 5th ed, Columbus, Ohio: Merrill Publishing Company, 1994 K. Gopalan, Introduction to Digital Microelectronic Circuits, Chicago: Irwin, 1996. J. D. Greenfield, Practical Digital Design Using ICs, 3rd ed, Englewood Cliffs, N.J.: Prentice-Hall, 1994 R J Prestopnik, Digital Electronics: Concepts and Applications for Digital Design, Philadelphia: Saunders College Publishing, 1990. R.S. Sandige, Modern Digital Design, New York: McGraw-Hill, 1990. M. Shoji, Theory of CMOS Digital Circuits and Circuit Failures, Princeton, N J: Princeton University Press, 1992. R J. Tocci, Digital Systems: Principles and Applications, 6th ed, Englewood Cliffs, N.J. Prentice-Hall, 1995 S. H Unger, The Essence of Logic Circuits, 2nd ed, New York: IEEE Press, 1996 J. F. Wakerly, Digital Design: Principles and Practices, 2nd ed, Englewood Cliffs, N J: Prentice-Hall, 1994 c2000 by CRC Press LLC
© 2000 by CRC Press LLC used to interface the circuits together if these voltage requirements are not met. Of course, a driving circuit’s output must not exceed the maximum and minimum allowable input voltages for the driven circuit. Also, the current sinking and sourcing ability of the driver circuit’s output must be greater than the total current requirements for the loading circuit. Buffer gates or stages must be used if current requirements are not satisfied. All chips within a single logic family are designed to be compatible with other chips in the same family. Mixing chips from multiple subfamilies together within a single digital circuit can have adverse effects on the overall circuit’s switching speed and noise immunity. Defining Terms Fan-out: The specification used to identify the limit to the number of loading inputs that can be reliably driven by a driving device’s output. Logic level: The high or low value of a voltage variable that is assigned to be a 1 or a 0 state. Noise immunity: A logic device’s ability to tolerate input voltage fluctuation caused by noise without changing its output state. Propagation delay time: The time delay from when the input logic level to a device is changed until the resultant output change is produced by that device. Speed-power product: An overall performance measurement that is used to compare the various logic families and subfamilies. Truth table: A listing of the relationship of a circuit’s output that is produced for various combinations of logic levels at the inputs. Related Topic 25.3 Application-Specific Integrated Circuits References A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Boston: Kluwer Academic, 1995. D. J. Comer, Digital Logic and State Machine Design, 2nd ed., Philadelphia: Saunders College Publishing, 1990. S. H. K. Embabi, A. Bellaouar, and M. I. Elmasry, Digital BiCMOS Integrated Circuit Design, Boston: Kluwer Academic, 1993. T. L. Floyd, Digital Fundamentals, 5th ed., Columbus, Ohio: Merrill Publishing Company, 1994. K. Gopalan, Introduction to Digital Microelectronic Circuits, Chicago: Irwin, 1996. J. D. Greenfield, Practical Digital Design Using ICs, 3rd ed., Englewood Cliffs, N.J.: Prentice-Hall, 1994. R. J. Prestopnik, Digital Electronics: Concepts and Applications for Digital Design, Philadelphia: Saunders College Publishing, 1990. R. S. Sandige, Modern Digital Design, New York: McGraw-Hill, 1990. M. Shoji, Theory of CMOS Digital Circuits and Circuit Failures, Princeton, N.J.: Princeton University Press, 1992. R. J. Tocci, Digital Systems: Principles and Applications, 6th ed., Englewood Cliffs, N.J.: Prentice-Hall, 1995. S. H. Unger, The Essence of Logic Circuits, 2nd ed., New York: IEEE Press, 1996. J. F. Wakerly, Digital Design: Principles and Practices, 2nd ed., Englewood Cliffs, N.J.: Prentice-Hall, 1994. FIGURE 79.6 Circuit interfacing requirements