A Tool for Memory Protection Page tables with permission bits SUP READ WRITE Address Physical memory VP 0: no no Process i: VP no s yes 吧吧 64 PP O VP2 yes yesyes PP2 PP 2 PP 4 PP 6 SUP READ WRITE Addres VP 0: no ves no P PP 9 Process j: VP es es PP 6 VP2: no yes PP 11 PP 11 yes Figure 10.11 P704
16 A Tool for Memory Protection Figure 10.11 P704
10.7 Case Study: The Pentium/Linux Memory System
17 10.7 Case Study: The Pentium/Linux Memory System
P6 Memory Syste 32 bit address space DRAM external 4 KB page size system bus L1L2 and tlBs (e.g. PCl) 4-way set associative 2 inst tlB L2 32 entries cache 8 sets cache bus data tlB 64 entries bus interface unit 1) inst ·16sets TLB L1 i-cache and d-cache data 16 KB instruction)L1 TLB ·32 B line size fetch unit i-cache ·128sets L2 cache d-cache nified processor package ·128KB-2MB ·32 B line size 18 Figure 10.22 P716
18 bus interface unit DRAM external system bus (e.g. PCI) instruction fetch unit L1 i-cache L2 cache cache bus L1 d-cache inst TLB data TLB processor package • 32 bit address space • 4 KB page size • L1, L2, and TLBs • 4-way set associative • inst TLB • 32 entries • 8 sets • data TLB • 64 entries • 16 sets • L1 i-cache and d-cache • 16 KB • 32 B line size • 128 sets • L2 cache • unified • 128 KB -- 2 MB • 32 B line size P6 Memory System Figure 10.22 P716 2 1 3 1) 2) 4) 3)
10.7.1 Pentium Address Translation
19 10.7.1 Pentium Address Translation
P6 Address Translation CPU result L2 and DraM VPN VPo Virtual address (VA) L1 L1 hit mIss TLBTITLBI TLB L1(128 sets, 4 lines/set) TLB hit MIss ■■ TLB(16 sets, PN1VPN2 4 entries/set) 20 PPN PPO CT Cl CO 匚PDEL-PTE physical address(PA) pdb Page tables Figure 10.23 P717
20 CPU VPN VPO 20 12 TLBT TLBI 16 4 virtual address (VA) ... TLB (16 sets, VPN1 VPN2 4 entries/set) 10 10 PDE PTE PDBR PPN PPO 20 12 Page tables TLB miss TLB hit physical address (PA) result 32 ... CT CO 20 5 CI 7 L2 and DRAM L1 (128 sets, 4 lines/set) L1 hit L1 miss P6 Address Translation Figure 10.23 P717