D1.5 Virtualization16 Virtualization model Hypervisor runs in EL2 and Non-secure state, that is responsible for switchingbetweenvirtualmachinesVirtual machinehas Non-secure EL1 and ELOGuestOSsruninNon-secureELl onavirtualmachineApplications run in Non-secure ELO on a virtual machineVirtualizationexceptionsHypervisor Call (HVC)exceptionto EL2TrapstoEL2Virtual interrupts (Virtual Serror/IRQ/FIQ)to EL2ARM052019-3-17
D1.5 Virtualization ARM05 2019-3-17 16 Virtualization model Hypervisor runs in EL2 and Non-secure state, that is responsible for switching between virtual machines Virtual machine has Non-secure EL1 and EL0 Guest OSs run in Non-secure EL1 on a virtual machine Applications run in Non-secure EL0 on a virtual machine Virtualization exceptions Hypervisor Call (HVC) exception to EL2 Traps to EL2 Virtual interrupts (Virtual Serror/IRQ/FIQ) to EL2
D1.6 SLRegisters17XOX8voV8V24X16X24V16X1X9V1X17X25V9V17V25X2V2X10X18X26V10V18V26X3X11V3V11V19V27X19X27X4X12X20X28V4V12V20V28X5X13X21X29V5V13V21V29X6V6X14X22V14V22V30X30*(XZR)X7V7X15X23V15V23V31ELOEL1EL2EL3SP=StackPtrSP ELOSP EL1SPEL2SPEL3ELR=ExceptionELR EL1ELR_EL2ELR_EL3(PC)XLink RegisterSaved/CurrentSPSR EL3SPSR EL1SPSR_EL2(PSTATE)XProcess Status(CPSR)RegisterARM052019-3-17
D1.6 SL Registers ARM05 2019-3-17 17 (XZR) × × (PSTATE) (CPSR)
D1.6 SL Registers (cont)18 D1.6.1 GPRs D1.6.2 SPsD1.6.3 SIMD&FP口 D1.6.4 SPSRs D1.6.5 ELRsARM052019-3-17
D1.6 SL Registers (cont) ARM05 2019-3-17 18 D1.6.1 GPRs D1.6.2 SPs D1.6.3 SIMD&FP D1.6.4 SPSRs D1.6.5 ELRs
D1.6.1 GPRs19Itcomprises31GPRs,RO-R30 These registerscanbeaccessed as3164-bit registers,X0-X303132-bitregisters,W0-W30ARM052019-3-17
D1.6.1 GPRs ARM05 2019-3-17 19 It comprises 31 GPRs, R0-R30 These registers can be accessed as: 31 64-bit registers, X0-X30 31 32-bit registers, W0-W30
D1.6.2 SPs20DedicatedSPisusedforeachExceptionlevelSPELO.SPEL1,SPEL2,SPEL3PEcanbeconfiguredtouseSPELOorSP_ELxPSTATE.SP=O,SP_ELO;PSTATE.SP=1,SP ELxSelected SP is indicatedby a suffixto ELTableD1-2AArch64stackpointeroptionstIndicatesSPELOExceptionlevelAArch64stackpointeroptionshIndicatesSPELxELOELotEL1ELlt,ELihEL2EL2t.EL2hEL3EL3t,EL3hARM052019-3-17
D1.6.2 SPs ARM05 2019-3-17 20 Dedicated SP is used for each Exception level SP_EL0, SP_EL1, SP_EL2, SP_EL3 PE can be configured to use SP_EL0 or SP_ELx PSTATE.SP=0, SP_EL0; PSTATE.SP=1, SP_ELx Selected SP is indicated by a suffix to EL t Indicates SP_EL0 h Indicates SP_ELx