D1.2.1Precise&lmpreciseexceptionsAnexceptionisdescribed asprecisewhentheexceptionhandlerreceives the PEstateand memory system state,that is consistent withthe PEhaving executed all of the instructions up to but not includingthe point in the instruction stream where the exception was taken, andnoneafterwards On the contrary itisdescribed as impreciseARMO52019-3-17
D1.2.1 Precise&Imprecise exceptions ARM05 2019-3-17 11 An exception is described as precise when the exception handler receives the PE state and memory system state, that is consistent with the PE having executed all of the instructions up to but not including the point in the instruction stream where the exception was taken, and none afterwards On the contrary it is described as imprecise
D1.2.2Sync&Asyncexceptions12An exception is described as synchronous iflsdirectresultofinstructionexecutionRet_addrindicates instructionthatcausedexceptionTheexceptionispreciseAn exception is described as asynchronousifIsnotdirectresultofinstructionexecutionRet_addr notindicate instructionthatcaused exceptionThe exceptionis impreciseARMO52019-3-17
D1.2.2 Sync&Async exceptions ARM05 2019-3-17 12 An exception is described as synchronous if Is direct result of instruction execution Ret_addr indicates instruction that caused exception The exception is precise An exception is described as asynchronous if Is not direct result of instruction execution Ret_addr not indicate instruction that caused exception The exception is imprecise
D1.3Executionstates13Executionstatecategories口AArch64:The 64-bitExecutionstateAArch32:The32-bitExecution stateExecutionstateusageEL0/EL1/EL2useAArch64/AArch32EL3uses AArch64Execution statetransitionAtresetOna changeof ExceptionlevelARM052019-3-17
D1.3 Execution states ARM05 2019-3-17 13 Execution state categories AArch64: The 64-bit Execution state AArch32: The 32-bit Execution state Execution state usage EL0/EL1/EL2 use AArch64/AArch32 EL3 uses AArch64 Execution state transition At reset On a change of Exception level
D1.4Securitystates4 Securitystatecategories Secure statePEcanaccessSecureandNon-securephysicaladdressspaceNon-secure statePEcanonlyaccessNon-securephysicaladdressspaceSecuritystateusageEL3existsonlyinSecurestateAchangefromNon-securestatetoSecurestatecanonlyoccurontakinganexceptiontoEL3Achange from Secure state toNon-secure state can only occur on an exception return fromEL3 EL2 it exists only in Non-secure stateEL1andELOarepresent inbothSecuritystatesARM052019-3-17
D1.4 Security states ARM05 2019-3-17 14 Security state categories Secure state ◼ PE can access Secure and Non-secure physical address space Non-secure state ◼ PE can only access Non-secure physical address space Security state usage EL3 exists only in Secure state ◼ A change from Non-secure state to Secure state can only occur on taking an exception to EL3 ◼ A change from Secure state to Non-secure state can only occur on an exception return from EL3 EL2 it exists only in Non-secure state EL1 and EL0 are present in both Security states
Non-securestateSecure stateAArch32orAArch32orAArch32orAArch32orAArch32orAArch32orAArch64tAArch64tAArch64tAArch64tAArch64tAArch64tELOApp1App2App1App2SecureApp1SecureApp2AArch32orAArch64AArch32orAArch64*AArch32orAArch64EL1GuestOS1GuestOs2SecureOsAArch32orAArch64EL2HypervisorAArch64EL3SecuremonitortAArch64permittedonlyifEL1isusingAArch64 AArch64 permitted only if EL2 is using AArch6415FigureD1-1ARMv8-AsecuritymodelwhenEL3isusingAArch64
15 ARM05 2019-3-17