D1.6.3SIMD&FP21Itcomprises32 128-bitregisters,V0-V31 These registers canbe accessed as:32 scalar orvectorregisters32 doubleword (64-bit) registers, D0-D3132 word (32-bit) registers, S0-S3132 halfword (16-bit)registers,HO-H3132 byte(8-bit)registers, BO-B31ARM052019-3-17
D1.6.3 SIMD&FP ARM05 2019-3-17 21 It comprises 32 128-bit registers, V0-V31 These registers can be accessed as: 32 scalar or vector registers 32 doubleword (64-bit) registers, D0-D31 32 word (32-bit) registers, S0-S31 32 halfword (16-bit) registers, H0-H31 32 byte (8-bit) registers, B0-B31
D1.6.4 SPSRs22 SPSRs (Saved Program Status Registers)save PE state on takingexceptionsThereisaSPSRateachELexceptionsSPSR_ELo, Exceptions cannot be taken to ELoSPSR_EL1,forexceptionstakentoELlSPSR_EL2,forexceptionstakentoEL2SPSR_EL3,forexceptionstakentoEL3WhenthePEtakesanexception,PEstateissavedintheSPSRattheExceptionleveltheexceptionistakento,andwhenexceptionreturnson the contraryARM052019-3-17
D1.6.4 SPSRs ARM05 2019-3-17 22 SPSRs (Saved Program Status Registers) save PE state on taking exceptions There is a SPSR at each EL exceptions SPSR_EL0, Exceptions cannot be taken to EL0 SPSR_EL1, for exceptions taken to EL1 SPSR_EL2, for exceptions taken to EL2 SPSR_EL3, for exceptions taken to EL3 When the PE takes an exception, PE state is saved in the SPSR at the Exception level the exception is taken to, and when exception returns on the contrary
SPSRs23Foran exceptiontaken toAArch64 state fromAArch64 state.theSPSRbit assignments are:31302928272423222120|19109876543210RESORESORESOM[3:0]-IL-M[4].ExecutionStatessRESOMaskbitsModebitsConditionflagsFor an exception taken toAArch64 statefromAArch32 state.the SPSR bit assignments are:2120|1916156543031302928272625242310987RESOGE[3:0]IT[7:2]M[3:0]NZCL IT[1:0]LILL-M[4].Execution StatessMaskbitsModebitsCondition flagsARM052019-3-17
SPSRs ARM05 2019-3-17 23
28127242322212019NzovRESORESOM[3:0]RESOLILLM[4].Execution State-SSRESOMode bitsConditionflagsMaskbits24Condition flags N, bit[31] Negative condition flag Z, bit[30] Zero condition flag C, bit[29] Carry condition flag V, bit[28] Overflow condition flagARM052019-3-17
ARM05 2019-3-17 24 Condition flags N, bit[31] Negative condition flag Z, bit[30] Zero condition flag C, bit[29] Carry condition flag V, bit[28] Overflow condition flag
24123231302928/22120|19RESONZCRESORESOM[3:0]LILL-M[4].ExecutionStateSSRESOModebitsConditionflagsMaskbits25 RESO (Reserved)ForexceptionstakenfromAArch64ForexceptionstakenfromAArch32QShowsthevalueofPSTATE.QimmediatelybeforetheexceptionwastakenIT[1:0] See Bits[19:10]JShowsthevalueofPSTATE.JimmediatelybeforetheexceptionwastakenARM052019-3-17
ARM05 2019-3-17 25 RES0 (Reserved) For exceptions taken from AArch64 For exceptions taken from AArch32 Q Shows the value of PSTATE.Q immediately before the exception was taken IT[1:0] See Bits[19:10] J Shows the value of PSTATE.J immediately before the exception was taken