9.3.1用可综合的Verilog模块设计状态机的典型办法SALISTOTONGmodule fsm (Clock, Reset, A,F, G);inputClock,Reset,A;outputF,G;reg F,G;reg [1:0] state;parameter Idle =2'b00,Start=2'b01,Stop=2'b10,Clear =2'b11;例1172025/12/3
2025/12/3 17 9.3.1 用可综合的Verilog模块 设计状态机的典型办法 module fsm (Clock, Reset, A, F, G); input Clock, Reset, A; output F,G; reg F,G; reg [1:0] state ; parameter Idle = 2’b00, Start = 2’b01, Stop = 2’b10, Clear = 2’b11; 例1
Stop:beginalways@(posedgeClock)if(IReset)if (A)begin1909beginstate<= Clear;大TF <= 1;state<=ldle;F<=0;G<=0OTONGendendelseelse state<=Stop;endcase (state)idle:beginClear:beginif(A)beginif (!A)beginstate<=Start;state<=ldle;G<=0;F<=0; G<=1;endendelsestate<=idle;else state<=Clear;endendstart:beginendcaseif(!A)state<=Stop;endmoduleelsestate<=start;end182025/12/3
2025/12/3 18 always @(posedge Clock) if (!Reset) begin state <= Idle; F<=0; G<=0; end else case (state) idle: begin if (A) begin state <= Start; G<=0; end else state <= idle; end start: begin if (!A) state <= Stop; else state <= start; end Stop: begin if (A) begin state <= Clear; F <= 1; end else state <= Stop; end Clear: begin if (!A) begin state <=Idle; F<=0; G<=1; end else state <= Clear; end endcase endmodule