例:用case语句描述四选一电路 library ieee use ieee std logic 1164.alli entity mux is port(a, b, io, il, 12, 13:in std logici g: out std logic)i end mux: architecture muxi behave of mux 4 is signal sel: std logic vector(l downto 0)i begin process(a,b, 1o, il, 12, 13) begin sel<=b & a case sel is When"00"=><=10:when"01"=>(<=11 when"10"=>q<=i2;when"11"=><=i3; when others =>X end case end process end mux behave
26 例：用case 语句描述四选一电路
例:case语句的误用 signal value: integer range o to 15 signal out_1: bit case value is 缺少when条件语句 end case case value Is 分支条件不包含2到15 when 0=> out 1 when 1=> out 1<=0 end case case value Is 在5到10上发生重叠 when 0 to 10=> out 1<=1 when5to15=out1<=“0 en d case
27 例：case 语句的误用 signal value:integer range 0 to 15; signal out_1 : bit ; case value is -- 缺少 when条件语句 end case ; case value is -- 分支条件不包含2到15 when 0 => out_1 <= ‘1’ ; when 1 => out_1 <=‘0’ ; end case ; case value is -- 在5到10上发生重叠 when 0 to 10 => out_1 <= ‘1’ ; when 5 to 15 => out_1 <= ‘0’ ; end case ;
例:根据输入确定输出值 library ieee use ieeestd_logic_1164.all entity mux4l is port(s4, S3, S2, sl: in std_logic 44, Z3, Z2, Z1: out std_logic) end mux41 architecture art of mux41 is begin process(s4, S3, S2, S1) variable sel: integer range oto 15 begin sel: =0
28 例：根据输入确定输出值 library ieee; use ieee.std_logic_1164.all; entity mux41 is port(s4,s3,s2,s1: in std_logic; z4,z3,z2,z1: out std_logic); end mux41; architecture art of mux41 is begin process(s4, s3, s2, s1) variable sel: integer range 0to15; begin sel:=0;
if s1=1 then sel: =sel+1, end if if s2=1 then sel: =sel +2: end if ifs3=-1’ then se∷:=sel|+4; end if; if s4="1 then sel: =sel+8: end if Z1<=0;22<=0;23<=0;z4<=“0; case sel is When 0=>z1<=1 When1|3=>z2<=1 When 4 to 72=>Z3<=<1 When others =>74<=1 en d case end process end art: 29
29 if s1=‘1’ then sel:=sel+1; end if; if s2=‘1’ then sel:=sel+2; end if; if s3=‘1’ then sel:=sel+4; end if; if s4=‘1’ then sel:=sel+8; end if; z1<=‘0’; z2<=‘0’; z3<=‘0’; z4<=‘0’; case sel is when 0 =>z1<=‘1’; when 1|3 =>z2<=‘1’; when 4 to 7|2 =>z3<=‘1’; when others =>z4<=‘1’; end case; end process; end art;
3、Loop 语句 oop语句与其它高级语言中的循环语句相似 Loop语句有三种格式 1)无限loop语句 loop label]: LOOP --sequential statement EXIT loop label END LOOP VHDL重复执行loop循环内的语句 直至遇到exit语句结束循环
30 3、Loop 语句 loop 语句与其它高级语言中的循环语句相似。 Loop 语句有三种格式。 1）无限 loop 语句 VHDL重复执行 loop 循环内的语句， 直至遇到 exit 语句结束循环。 [loop_label]：LOOP --sequential statement EXIT loop_label ; END LOOP;