COUNT:STD LOGIC_VECTOR)return STD LOGIC_VECTOR;endSTDLOGIC UNSIGNEDLIBRARYIEEE;程序包体use IEEE.std _logic_1164.all ;use IEEE.std_ logic_arith.all ;packagebodySTDLOGIC_UNSIGNEDisfunction maximum (L, R:INTEGER) returnINTEGERisbeginifLR then return L;elsereturn R;end if,end;function"+"(L:STD LOGIC VECTOR;R:INTEGER)returnSTD_LOGIC_VECTORisVariable result : STD_LOGIC_VECTOR (L'range);Beginresult :=UNSIGNED(L) +R ;return std_ logic_vector(result) ;end ;endSTDLOGIC_UNSIGNED ;8.3.3VHDL转换函数表8-1IEEE库类型转换函数表功能函数名程序包：STD_LOGIC_1164to_stdlogicvector(A)由bit_vector类型的A转换为std_logic_vectorto_bitvector(A)由std_logic_vector转换为bit_vector由bit转换成std_logicto_stdlogic (A)to_bit(A)由std_logic转换成bit程序包：STDLOGIC_ARITH将整数integer转换成stdlogic_vector类型，A是convstdlogic_vector(A，位长）将stdlogic_vector转换成整数integerconv_integer(A)程序包：STDLOGICUNSIGNED由std_logic_vector转换成integerconv_integer(A)6
6 COUNT : STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR ; . end STD_LOGIC_UNSIGNED ; LIBRARY IEEE ; - 程序包体 use IEEE.std_logic_1164.all ; use IEEE.std_logic_arith.all ; package body STD_LOGIC_UNSIGNED is function maximum (L, R : INTEGER) return INTEGER is begin if L R then return L; else return R; end if; end; function "+" (L : STD_LOGIC_VECTOR ; R : INTEGER) return STD_LOGIC_VECTOR is Variable result : STD_LOGIC_VECTOR (L’range) ; Begin result := UNSIGNED(L) + R ; return std_logic_vector(result) ; end ; . end STD_LOGIC_UNSIGNED ； 8.3.3 VHDL 转换函数 表 8-1 IEEE 库类型转换函数表 函数名 功能 程序包: STD_LOGIC_1164 to_stdlogicvector(A) 由 bit_vector 类型的 A 转换为 std_logic_vector to_bitvector(A) 由 std_logic _vector 转换为 bit_vector to_stdlogic (A) 由 bit 转换成 std_logic to_bit(A) 由 std_logic 转换成 bit 程序包: STD_LOGIC_ARITH conv_std_logic_vector(A, 位长) 将整数 integer 转换成 std_logic_vector 类型，A 是 整数 conv_integer(A) 将 std_logic_vector 转换成整数 integer 程序包: STD_LOGIC_UNSIGNED conv_integer(A) 由 std_logic_vector 转换成 integer
【例8-5】LIBRARY IEEE:USE IEEE. std_logic_1164.ALL;ENTITY exg ISPORT (a,b : in bit_vector(3 downto O),: out std_logic_vector(3 downto 0);qend ;architecture rtl of exg isbeginq<=to_stdlogicvector(a andb);--将位失量数据类型转换成标准逻辑位矢量数据end;【例8-6]LIBRARYIEEE:USEIEEE.STD LOGIC 1164.ALL:USEIEEE.STD_LOGIC_ARITH.ALL;--注意使用了此程序包ENTITYaxamp ISPORT(a,b,c : IN integer range O to 15 ;:OUTstd_logic_vector(3downto0));qEND;ARCHITECTURE bhv OF axampISBEGINq<=conv_std_logic_vector(a,4)whenconv_integer(c)=8 elseconv_std_logic_vector(b,4);END;8.3.4VHDL过程过程首PROCEDURE过程名（参数表）PROCEDURE过程名（参数表）IS[说明部分]BIGIN过程体顺序语句；ENDPROCEDURE过程名PROCEDUREprol(VARIABLE a,b:INOUTREAL):PROCEDUREEpro2(CONSTANTal:ININTEGER;b1OUTVARIABLEINTEGER);PROCEDUREpro3(SIGNAL sig:INOUTBIT);7
7 【例 8-5】 LIBRARY IEEE; USE IEEE. std_logic_1164.ALL; ENTITY exg IS PORT (a,b : in bit_vector(3 downto 0); q : out std_logic_vector(3 downto 0)); end ; architecture rtl of exg is begin q<= to_stdlogicvector(a and b);-将位矢量数据类型转换成标准逻辑位矢量数据 end; 【例 8-6】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;-注意使用了此程序包 ENTITY axamp IS PORT(a,b,c : IN integer range 0 to 15 ; q : OUT std_logic_vector(3 downto 0) ); END; ARCHITECTURE bhv OF axamp IS BEGIN q <= conv_std_logic_vector(a,4) when conv_integer(c)=8 else conv_std_logic_vector(b,4) ; END; 8.3.4 VHDL 过程 PROCEDURE 过程名(参数表) - 过程首 PROCEDURE 过程名(参数表) IS [说明部分] BIGIN - 过程体 顺序语句; END PROCEDURE 过程名 PROCEDURE pro1 (VARIABLE a, b : INOUT REAL) ; PROCEDURE pro2 (CONSTANT a1 : IN INTEGER ； VARIABLE b1 : OUT INTEGER ) ; PROCEDURE pro3 (SIGNAL sig : INOUT BIT) ;
【例8-8】PROCEDUREEprg1(VARIABLEvalue:INOUTBIT_VECTOR(OTO7)ISBEGINCASE value ISWHEN"0000"=>value:"0101";WHEN"0101"=>value:"0000";WHENOTHERS=>value:"1III":ENDCASE:ENDPROCEDUREprgl ;【例8-9]PROCEDUREcomp(a,r:INREAL:m:ININTEGER:v1, v2: OUT REAL)ISVARIABLEcnt :INTEGER;BEGINvl :=1.6*a;赋初始值v2 := 1.0;赋初始值Ql: FOR cnt INLOOP1TOmv2 := v2 * vl ;EXITQIWHENv2>vl;--当v2>v1，跳出循环LOOPENDLOOPQIASSERT (v2<v1)REPORT"OUTOFRANGE"输出错误报告SEVERITY ERROR;END PROCEDUREcomp【例8-10】LIBRARYIEEE:USEIEEE.STD LOGIC1164.ALL:PACKAGE axamp IS--过程首定义PROCEDURE nand4a (SIGNAL a,b,c,d:IN STD LOGIC;SIGNAL y:OUT STD_LOGIC),END axamp,--过程体定PACKAGEBODYaxampIS义PROCEDUREnand4a(SIGNALa,b,c,d:INSTDLOGIC;SIGNALy:OUT STD LOGIC)ISBEGINy<= NOT(a AND b AND c AND d);RETURN;8
8 【例 8-8】 PROCEDURE prg1(VARIABLE value:INOUT BIT_VECTOR(0 TO 7)) IS BEGIN CASE value IS WHEN "0000" => value: "0101" ; WHEN "0101" => value: "0000" ; WHEN OTHERS => value: "1111" ; END CASE ; END PROCEDURE prg1 ; 【例 8-9】 PROCEDURE comp ( a, r : IN REAL; m : IN INTEGER ; v1, v2: OUT REAL) IS VARIABLE cnt : INTEGER ; BEGIN v1 := 1.6 * a ; - 赋初始值 v2 := 1.0 ; - 赋初始值 Q1 : FOR cnt IN 1 TO m LOOP v2 := v2 * v1 ; EXIT Q1 WHEN v2 > v1; - 当 v2 > v1，跳出循环 LOOP END LOOP Q1 ASSERT (v2 < v1 ) REPORT "OUT OF RANGE" - 输出错误报告 SEVERITY ERROR ; END PROCEDURE comp ; 【例 8-10】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; PACKAGE axamp IS -过程首定义 PROCEDURE nand4a (SIGNAL a,b,c,d : IN STD_LOGIC ; SIGNAL y : OUT STD_LOGIC ); END axamp; PACKAGE BODY axamp IS -过程体定 义 PROCEDURE nand4a (SIGNAL a,b,c,d : IN STD_LOGIC ; SIGNAL y : OUT STD_LOGIC ) IS BEGIN y<= NOT(a AND b AND c AND d); RETURN;