DSP结构：ASPProcessor ComponentsControllerDatapathControlRegisterslogic andStateInterconnectData PathregisterCustomALUProcessingProcessingPCIRUnitUnitDatamemoryProgrammemoryAssembly codefor:InstructionMemorytotal=0fori=l to...ProcessingManagementUnitUnit16/87Ilxx@ustc.edu.cn
DSP结构：ASP llxx@ustc.edu.cn 16/87
Characteristics of DSP's·CISC &RISC.Harvard- OneprogramfetchandmultipledataRWineachinstructioncycleMultiplebusseswithrestrictedconnectivityHigh l/O-rateIrregularregister setsof different sizesSpecial purpose registersSpecialregistersforzero-overhead loopsMultiply-add-accumulate in one instruction- Single cycle multiply-accumulate (MAC)·Fixed-pointoperations· Hardware supported addressing modes-Registerindirectaddressingwithpost-incrementBit-reversaladdressingforFFTModuloaddressingforhardwarecircularbuffers17/87Ilxx@ustc.edu.cn
Characteristics of DSP’s • CISC & RISC • Harvard – One program fetch and multiple data R/W in each instruction cycle • Multiple busses with restricted connectivity • High I/O-rate • Irregular register sets of different sizes • Special purpose registers llxx@ustc.edu.cn 17/87 • Special registers for zero-overhead loops • Multiply-add-accumulate in one instruction – Single cycle multiply-accumulate（MAC） • Fixed-point operations • Hardware supported addressing modes – Register indirect addressing with post-increment – Bit-reversal addressing for FFT – Modulo addressing for hardware circular buffers
DSP的特殊指令Sum-of-products operation for one data is executed in two cyclesGeneral multiply processing also is executed in three cyclesusingahigh-speedhardwaremultiplier8040~70bLEblt70272X+ 81F(x)=EC(n)*e60n50AO +20~~40403020The high-speedHardware mulfiplier-1021TT(0zbitsinMlec/en)H16C/60H16C/80DSPCECNCUCECNCUH32C/83WithWithoutmultipliermultiplier
DSP的特殊指令 llxx@ustc.edu.cn 18/87
DSP的低功耗策略P= Pam + Pse + Pu = 0.5CtVDD’Af + IseVDDA+ IuVDD·PowerManagementRISCUserDefinedMicroprocessoLogic- Gated clock1ORe-ConfiguableDSPLogic-Poweroffun-usedpartsRAM-Reduceclockrateof idleparts. Variable Instruction Length·CompressedInstruction· Full-Custom Data Path Layout: Technology and Voltage Scaling19/87Ilxx@ustc.edu.cn
DSP的低功耗策略 • Power Management – Gated clock – Power off un-used parts dyn sc lk L DD sc DD lkVDD P P P P C V Af I V A I 2 0.5 llxx@ustc.edu.cn 19/87 – Reduce clock rate of idle parts • Variable Instruction Length • Compressed Instruction • Full-Custom Data Path Layout • Technology and Voltage Scaling
TITMS320C55x：多总线DataReadbusesBB,CB,DB(3x16)/(3x24)DataReadAddressbusesBABCAB.DAB杯ProgramAddressbusPAB(24)C55xDSPCorePogramCcuntesAUEProg.FitrurtibinBudatMACMACRead busQusPB(atxabroTETACOEACOACYAC2ACS37AubisProg Aidress GenA0bitALUIretnutieenDecedeSuatus PogistarecheterCorarsllerProgramFlow1zndTmnsition RegsricheemerictionPpeline Protecticn UntBitOperetionsALUSNEntenupisDataWriteAddressbusesEAB,FAB(2x24)DataWritebusesEB.FB(2x16)
TI TMS320C55x：多总线 llxx@ustc.edu.cn 20/87