Using FPGAField Programmable Gate ArraySwtchBodkLogic BlodkWire Segrrent900电ese700e5003001OLIA100200420062008201020122014201620002002YearProgr&mmableSwitchWireSegmentModernFPGAchipsallowdynamicpartialreconfiguration(DPR)toreconfigureanFPGAareacontainingabout25%ofthetotalresourcesinlessthan3ms
Using FPGAField Programmable Gate Array • Modern FPGA chips allow dynamic partial reconfiguration (DPR) – to reconfigure an FPGA area containing about 25% of the total resources in less than 3ms
SOC EraASICEraSoCEraMPSoCEra198519952005upupuPRLogictMemMemMemuPIPLogicuPupIPLoaic1MemMemMem1D0CIPLogic2upDSPDSPDSPLogict-DSPMemMeMemIPLogic3IPLogicaicASIPASIPASIPMemoryMemoryoic'IPLogicMemMemMemoCTCDual/tripple-Multiple-ProcessorSingle-ProcessorASICSocProcessorSocSoc
SOC Era
Architecture for SOC-based ESChipSRAMChip CoreFlashGPIOUARTIBusSDRAMFlash
Architecture for SOC-based ES
SOC(System on Chip) 结构RISCUserDefinedLogicMicroprocessorIORe-ConfigurableDSPLogicRAM14/87llxx@ustc.edu.cn
SOC(System on Chip) 结构 llxx@ustc.edu.cn 14/87
DSP v.s. DSP !?: Digital Signal Processing- Mathematical manipulation of digitally representedsignals: Digital Signal Processor-MicroprocessorsdesignedtoperformDigital SignalProcessing:Real-timeperformance.Shorttime-to-market.Upgradablesolutions-MoveHardwareDesign (ASiC)to SoftwareDesign(Programming)- Offer the key to SOC integration15/87Ilxx@ustc.edu.cn
DSP v.s. DSP !? • Digital Signal Processing – Mathematical manipulation of digitally represented signals • Digital Signal Processor – Microprocessors designed to perform Digital Signal Processing llxx@ustc.edu.cn 15/87 • Real-time performance • Short time-to-market • Upgradable solutions – Move Hardware Design (ASIC) to Software Design (Programming) – Offer the key to SOC integration