嵌入式处理器体系结构
嵌入式处理器体系结构
内容提要（实例）·嵌入式处理器概述·通用处理器体系结构-CISC-RISC·嵌入式处理器·I/O系统-中断-DMA
内容提要 • 嵌入式处理器概述（实例） • 通用处理器体系结构 – CISC – RISC • 嵌入式处理器 • I/O系统 – 中断 – DMA
Stanford STARMAC ProjectLowLevelCarbonFiberControl ProcessorTubingRobostixFiberglassHighLevelHoneycombControlProcessorStargateSBCPlastic TubeStrapsorPC/104GPSSuperstarIlBrushlessSonicRangerDCMotorsSRF08Axi2208/26Inertial MeasurementElectronicUnit(IMU)Speed3DMG-X1ControllerBatteryPhoenix25LithiumPolymerLIDARStereo VisionHokuyoVidereSystemsURG-04LXSmall VisionSystem
Stanford STARMAC Project
四旋翼飞控：STARMAC architectureLIDARRS232URG-04LX115kbpsPC/10410HzrangesWiFiUSB2PentiumM802.11g+1GBRAM,1.8GHZStereoCam480MbpsFirewire$54MbpsVidereSTOCEst.&controlRS232480Mbps30fps320x240GPSUARTStargate1.0SuperstarIl19.2kbpsWiFiIntelPXA25510HzCF802.11bUART64MBRAM.400MHz100MbpsS5MbpsUART115KbpsIMUSupervisorGPsUART3DMG-X1Robostix76or100Hz115kbpsAtmega128LowlevelcontrolRanger12CPPMSRF08100Hz400kbpsTAnalog13HzAltitudeRangerBeaconEsC&MotorsMini-AETracker/DTSTimingPhoenix-25.Axi2208/2610-50HzAltitudeAnalog1Hz
四旋翼飞控：STARMAC architecture
Typical Architecture for RTS嵌入式系统虽然复杂，但通用处理器的设计经验会有很大帮助oPeripheral BusDEBUGPortNon-volatile memoryCustom Devices*EPROM.FLASH.DISK·ASIC-Hybrid.FPGA.PALMicroprocessor.4,8,16,32,4bitbus.CISC,RISC,DSPStandardDevices-Integrated peripheralsVolatile Memory.1/OPorts.Debug/TestPort·DRAM,SRAM-PeripheralControllers.Caches-Hybrid-Pipeline.Multiprocessing SystemsCommunicationDevices·Ethemet-RS-232-SCSI-CentronicsSystemClocks-Proprietary.RTC circuitrySoftware-System clocks.Integratedin uC·ApplicationCodeMicroprocessorBus-Imported/Exported-DriverCode/BIOS-Real TimeOperatingSystem.Custom.UserInterface.PCI-CommunicationsProtocolStacks.VME.C.C++,AssemblyLanguage-PC-102-Legacy Code5/87Ilxx@ustc.edu.cn
Typical Architecture for RTS llxx@ustc.edu.cn 5/87