同桥大学 TONGJI UNIVERSITY Modular Sequential Logic
Modular Sequential Logic
同©大学 D Ao TONGJI UNIVERSITY R C 12 D A3 2002 Prentice Hall,Inc. Clock Clear M.Morris Mano DIGITAL DESIGN,3e. Fig.6-1 4-Bit Register
同桥大学 TONGJI UNIVERSITY Load A2 Clock Fig.6-2 4-Bit Register with Parallel Load 2002 Prentice Hall.Inc. M.Morris Mano DIGITAL DESIGN,3e
同桥大学 TONGJI UNIVERSITY Load decide whether to keep the state ●Load=0keep Load=1 receive new data
Load decide whether to keep the state ⚫Load=0 keep ⚫Load=1 receive new data
同桥大学 TONGJI UNIVERSITY Shift Registers Logic Design which manipulates the bit position of binary data by shifting it to the left or right. ●Major application OSerial Data to Parallel Data converters
Shift Registers ⚫Logic Design which manipulates the bit position of binary data by shifting it to the left or right. ⚫Major application Serial Data to Parallel Data converters