●●● 13.2 /0 Hardware ●●●● ●●●●● ●●●● ● Interrupts ●●●0● ●●●0 Disadvantage of polling Polling becomes inefficient when it rarely finds a device to be ready for service o It may be more efficient for controller to notify the CPU when the device becomes ready for service interrupt ● nterrupt mechanisn After executing every instruction, the CPU senses the interrupt-request line to find whether a control has asserted a signal on the line The CPu performs a state save and jumps to the interrupt-handler routine at a fixed address in memory
17 13.2 I/O Hardware ⚫ Interrupts ⚫ Disadvantage of polling ⚫ Polling becomes inefficient when it rarely finds a device to be ready for service ⚫ It may be more efficient for controller to notify the CPU when the device becomes ready for service ————interrupt ⚫ Interrupt mechanism ⚫ After executing every instruction, the CPU senses the interrupt-request line to find whether a control has asserted a signal on the line ⚫ The CPU performs a state save and jumps to the interrupt-handler routine at a fixed address in memory
●●● 13.2 /0 Hardware ●●●● ●●●●● ●●●● ●●●0● ● nterrupt handler ●●●0 determines the cause of interrupt Performs the necessary processing Performs a state restore Executes a return from interrupt instruction to return the cPu to the execution state prior to the interrupt receives interrupts The basic interrupt mechanism enables the CPU to respond to an asynchronous event
18 13.2 I/O Hardware ⚫ Interrupt handler ▪ determines the cause of interrupt ▪ Performs the necessary processing ▪ Performs a state restore ▪ Executes a return from interrupt instruction to return the CPU to the execution state prior to the interrupt ▪ receives interrupts ⚫ The basic interrupt mechanism enables the CPU to respond to an asynchronous event
●●● 13.2 /0 Hardware ●●●● ●●●●● ●●●● Interrupt-Driven I/o Cycl ●●●0● ●●●0 CPU yo controller device driver initiates v/o 2 initiates I/o CPU executing checks for interrupts between instructions CPU receiving interrupt, 4 input ready, output transfers control to complete, or error interrupt handler generates interrupt signal 5 interrupt handle processes data returns from interrupt 6 CPU resumes processing of interrupted task
19 13.2 I/O Hardware Interrupt-Driven I/O Cycle
●●● 13.2 /0 Hardware ●●●● ●●●●● ●●● o More complex interrupt features is needed in 8900 modern os o Be able to defer interrupt handling during critical processing o Need an efficient way to dispatch to the proper interrupt handler for device without polling all the devices to see which one raised the interrupt Be able to distinguish between high-priority and low- priority interrupts and respond with the appropriate degree of urgency - -these are provided by cpu and interrupt-controller hardware
20 13.2 I/O Hardware ⚫ More complex interrupt features is needed in modern OS ⚫ Be able to defer interrupt handling during critical processing ⚫ Need an efficient way to dispatch to the proper interrupt handler for device without polling all the devices to see which one raised the interrupt ⚫ Be able to distinguish between high-priority and lowpriority interrupts and respond with the appropriate degree of urgency ——these are provided by CPU and interrupt-controller hardware
●●● 13.2 /0 Hardware ●●●● ●●●●● ●●● Two interrupt request lines ●●●0● ●●●0 Nonmaskable interrupt line For events such as unrecoverable memory errors e Maskable interrupt line For device controllers It can be turned off by the cpu before the execution of critical instruction ● nterrupt vector Contains the memory addresses of specialized interrupt handlers Reduces the need for a interrupt handler to search all possible sources of interrupts
21 13.2 I/O Hardware ⚫ Two interrupt request lines ⚫ Nonmaskable interrupt line ▪ For events such as unrecoverable memory errors ⚫ Maskable interrupt line ▪ For device controllers ▪ It can be turned off by the CPU before the execution of critical instruction ⚫ Interrupt vector ⚫ Contains the memory addresses of specialized interrupt handlers ⚫ Reduces the need for a interrupt handler to search all possible sources of interrupts