13.20 Hardware ●●● ●●●● ●●●●● ●●● Device O Port Locations on PCs (partial).o0 ●●●● O address range(hexadecimal) device 000-00F DMA controller 020-021 interrupt controller 040-043 timer 200-20F game controller 2F8-2FF serial port (secondary) 320-32F hard-disk controller 378-37F parallel port 3D0-3DF graphics controller 3F0-3F7 diskette-drive controller 3F8-3FF serial port(primary)
12 13.2 I/O Hardware Device I/O Port Locations on PCs (partial)
●●● 13.2 /0 Hardware ●●●● ●●●●● ●●● ● nteraction protocol ●●●0● ●●●0 (Handshaking protocol between the host and a control) Three interaction models between l /o controllers and CPUs to accomplish an complete 0 transfer Polling(问答式) Interrupt DMA
13 13.2 I/O Hardware ⚫ Interaction protocol (Handshaking protocol between the host and a control) ⚫ Three interaction models between I/O controllers and CPUs to accomplish an complete I/O transfer ▪ Polling （问答式） ▪ Interrupt ▪ DMA
13.20 Hardware ●●● ●●●● ●●●●● ●●●● Polling ●●●0● ●●●0 Plo (programmed 0, Polling) ° An example e Two bits The busy bit in the status register indicates if the controller is busy or not The command -ready bit in the control command register indicates if the a command is available or not for the controller to execute
14 13.2 I/O Hardware ⚫ Polling ⚫ PIO (programmed I/O， Polling) ⚫ An example ⚫ Two bits ▪ The busy bit in the status register ▪ indicates if the controller is busy or not. ▪ The command-ready bit in the control/command register ▪ indicates if the a command is available or not for the controller to execute
●●● 13.2 /0 Hardware ●●●● ●●●●● ●●●● ● Handshaking mechanism works as follows"° ●● ( the host writes output through a port:|°° The host repeatedly reads the busy bit until that it becomes clear(busy waiting or polling) The host sets the writing bit(正在写) in the controllcommand register (availably for reading command) and writes a byte into the data-out register The host sets the command-ready bit in the controllcommand register
15 13.2 I/O Hardware ⚫ Handshaking mechanism works as follows (the host writes output through a port): ▪ The host repeatedly reads the busy bit until that it becomes clear (busy waiting or polling) ▪ The host sets the writing bit(正在写) in the control/command register (availably for reading command) and writes a byte into the data-out register ▪ The host sets the command-ready bit in the control/command register
●●● 13.2 /0 Hardware ●●●● ●●●●● ●●● When the controller notices that the ●●●0● ●●0 command-ready bit is set, it sets the busy bit (in status register) The controller reads the command register and gets the write command It reads the data out register to get the byte, and does the o to the device The controller clears the command-ready bit clears the error bit in the status register to indicate that the device o succeeded and clears the busy bit to indicate that it is finished
16 13.2 I/O Hardware ▪ When the controller notices that the command-ready bit is set, it sets the busy bit (in status register) ▪ The controller reads the command register and gets the write command. It reads the dataout register to get the byte, and does the I/O to the device. ▪ The controller clears the command-ready bit, clears the error bit in the status register to indicate that the device I/O succeeded, and clears the busy bit to indicate that it is finished